A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits
To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Co...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-06-01
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| Series: | Sensors |
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| Online Access: | https://www.mdpi.com/1424-8220/21/13/4462 |
| _version_ | 1797528354438512640 |
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| author | Malik Summair Asghar Saad Arslan Hyungwon Kim |
| author_facet | Malik Summair Asghar Saad Arslan Hyungwon Kim |
| author_sort | Malik Summair Asghar |
| collection | DOAJ |
| description | To realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm<sup>2</sup> chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation. |
| first_indexed | 2024-03-10T09:57:05Z |
| format | Article |
| id | doaj.art-c08232b5e2244a04acebf414c63d5a4b |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-03-10T09:57:05Z |
| publishDate | 2021-06-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-c08232b5e2244a04acebf414c63d5a4b2023-11-22T02:17:10ZengMDPI AGSensors1424-82202021-06-012113446210.3390/s21134462A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse CircuitsMalik Summair Asghar0Saad Arslan1Hyungwon Kim2Department of Electronics Engineering, Chungbuk National University, Chungdae-ro 1, Seowon-gu, Cheongju 28644, KoreaDepartment of Electrical and Computer Engineering, COMSATS University Islamabad, Park Road, Tarlai Kalan, Islamabad 45550, PakistanDepartment of Electronics Engineering, Chungbuk National University, Chungdae-ro 1, Seowon-gu, Cheongju 28644, KoreaTo realize a large-scale Spiking Neural Network (SNN) on hardware for mobile applications, area and power optimized electronic circuit design is critical. In this work, an area and power optimized hardware implementation of a large-scale SNN for real time IoT applications is presented. The analog Complementary Metal Oxide Semiconductor (CMOS) implementation incorporates neuron and synaptic circuits optimized for area and power consumption. The asynchronous neuronal circuits implemented benefit from higher energy efficiency and higher sensitivity. The proposed synapse circuit based on Binary Exponential Charge Injector (BECI) saves area and power consumption, and provides design scalability for higher resolutions. The SNN model implemented is optimized for 9 × 9 pixel input image and minimum bit-width weights that can satisfy target accuracy, occupies less area and power consumption. Moreover, the spiking neural network is replicated in full digital implementation for area and power comparisons. The SNN chip integrated from neuron and synapse circuits is capable of pattern recognition. The proposed SNN chip is fabricated using 180 nm CMOS process, which occupies a 3.6 mm<sup>2</sup> chip core area, and achieves a classification accuracy of 94.66% for the MNIST dataset. The proposed SNN chip consumes an average power of 1.06 mW—20 times lower than the digital implementation.https://www.mdpi.com/1424-8220/21/13/4462spiking neural networkleaky integrate and fireneuromorphicartificial neural networksartificial intelligenceimage classification |
| spellingShingle | Malik Summair Asghar Saad Arslan Hyungwon Kim A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits Sensors spiking neural network leaky integrate and fire neuromorphic artificial neural networks artificial intelligence image classification |
| title | A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits |
| title_full | A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits |
| title_fullStr | A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits |
| title_full_unstemmed | A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits |
| title_short | A Low-Power Spiking Neural Network Chip Based on a Compact LIF Neuron and Binary Exponential Charge Injector Synapse Circuits |
| title_sort | low power spiking neural network chip based on a compact lif neuron and binary exponential charge injector synapse circuits |
| topic | spiking neural network leaky integrate and fire neuromorphic artificial neural networks artificial intelligence image classification |
| url | https://www.mdpi.com/1424-8220/21/13/4462 |
| work_keys_str_mv | AT maliksummairasghar alowpowerspikingneuralnetworkchipbasedonacompactlifneuronandbinaryexponentialchargeinjectorsynapsecircuits AT saadarslan alowpowerspikingneuralnetworkchipbasedonacompactlifneuronandbinaryexponentialchargeinjectorsynapsecircuits AT hyungwonkim alowpowerspikingneuralnetworkchipbasedonacompactlifneuronandbinaryexponentialchargeinjectorsynapsecircuits AT maliksummairasghar lowpowerspikingneuralnetworkchipbasedonacompactlifneuronandbinaryexponentialchargeinjectorsynapsecircuits AT saadarslan lowpowerspikingneuralnetworkchipbasedonacompactlifneuronandbinaryexponentialchargeinjectorsynapsecircuits AT hyungwonkim lowpowerspikingneuralnetworkchipbasedonacompactlifneuronandbinaryexponentialchargeinjectorsynapsecircuits |