A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

A 2.5-GS/s Four-Way-Interleaved Ringamp-Based Pipelined-SAR ADC with Digital Background Calibration in 28-nm CMOS

A 2.5-GS/s 12-bit four-way time-interleaved pipelined-SAR ADC is presented in 28-nm CMOS. A bias-enhanced ring amplifier is utilized as the residue amplifier to achieve high bandwidth and excellent power efficiency compared with a traditional operational amplifier. A high linearity front-end is prop...

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Bibliographic Details
Main Authors:	Jingchao Lan, Danfeng Zhai, Yongzhen Chen, Zhekan Ni, Xingchen Shen, Fan Ye, Junyan Ren
Format:	Article
Language:	English
Published:	MDPI AG 2021-12-01
Series:	Electronics
Subjects:	analog-to-digital converter (ADC) ring amplifier time-interleaved ADC digital background calibration
Online Access:	https://www.mdpi.com/2079-9292/10/24/3173

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