Accelerating NoC Verification Using a Complete Model and Active Window

Accelerating NoC Verification Using a Complete Model and Active Window

This work presents formal modeling of Network-on-Chip (NoC) considering detailed functional units of NoC. The intricate modeling of NoC router components like buffer, switch, and arbiter is accomplished using Finite State Machine (FSM). As in the case of a real NoC, parallel execution of these funct...

Full description

Bibliographic Details
Main Authors: Surajit Das, Chandan Karfa, Santosh Biswas
Format: Article
Language:English
Published: IEEE 2022-01-01
Series:IEEE Access
Subjects:
Network-on-chip
formal model
model checking
finite state machine
starvation
Online Access:https://ieeexplore.ieee.org/document/9858921/

Similar Items

Similar Items