An Approach for a Wide Dynamic Range Low-Noise Current Readout Circuit
Designing low-noise current readout circuits at high speed is challenging. There is a need for preamplification stages to amplify weak input currents before being processed by conventional integrator based readout. However, the high current gain preamplification stage usually limits the dynamic rang...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2020-07-01
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| Series: | Journal of Low Power Electronics and Applications |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9268/10/3/23 |
| Summary: | Designing low-noise current readout circuits at high speed is challenging. There is a need for preamplification stages to amplify weak input currents before being processed by conventional integrator based readout. However, the high current gain preamplification stage usually limits the dynamic range. This article presents a 140 dB input dynamic range low-noise current readout circuit with a noise floor of 10 <inline-formula><math display="inline"><semantics><mrow><mi>f</mi><msub><mi>A</mi><mrow><mi>r</mi><mi>m</mi><mi>s</mi></mrow></msub><mo>/</mo><mi>s</mi><mi>q</mi><mrow><mo>(</mo><mi>H</mi><mi>z</mi><mo>)</mo></mrow></mrow></semantics></math></inline-formula>. The architecture uses a programmable bidirectional input current gain stage followed by an integrator-based analog-to-pulse conversion stage. The programmable current gains setting enables one to achieve higher overall input dynamic range. The readout circuit is designed and in 0.18 <inline-formula><math display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>m CMOS and consumes 10.3 mW power from a 1.8 V supply. The circuit has been verified using post-layout simulations. |
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| ISSN: | 2079-9268 |