Design and Implementation of a Low-Complexity Multi-<i>h</i> CPM Receiver with Linear Phase Approximation Synchronization Algorithm

Multi-<i>h</i> continuous phase modulation (CPM), with extremely high spectral efficiency, involves the plague of high demodulation complexity with a large number of matched filters and a complex trellis. In this paper, an efficient all-digital demodulator for multi-<i>h</i>...

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Main Authors: Le Wang, Huan Wen, Xucen Wu, Qingping Song
Format: Article
Language:English
Published: MDPI AG 2023-11-01
Series:Entropy
Subjects:
Online Access:https://www.mdpi.com/1099-4300/25/11/1530
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author Le Wang
Huan Wen
Xucen Wu
Qingping Song
author_facet Le Wang
Huan Wen
Xucen Wu
Qingping Song
author_sort Le Wang
collection DOAJ
description Multi-<i>h</i> continuous phase modulation (CPM), with extremely high spectral efficiency, involves the plague of high demodulation complexity with a large number of matched filters and a complex trellis. In this paper, an efficient all-digital demodulator for multi-<i>h</i> continuous phase modulation (CPM) is proposed based on a low-complexity decision-directed synchronization algorithm. Based on the maximum-likelihood estimation of the carrier phase and timing errors, we propose a reduced-complexity timing error detector with linear phase approximation (LPA) to the phase of the multi-<i>h</i> CPM. Compared with the traditional synchronization methods, it avoids derivative matched filtering and reduces about 2/3 of matched filters. The estimated accuracy and bit error rate (BER) performance of the LPA-based synchronization algorithm have no loss, as shown by the numerical simulation. Its stability is verified by the derived S-curve. Then, the receivers with the LPA-based synchronization for the three kinds of promising multi-<i>h</i> CPM are implemented on a Xilinx Kintex-7 FPGA platform. The experimental results show that the onboard tested BER of the proposed design has an ignorable loss in the numerical simulation. The implementation overhead on FPGA is significantly reduced by about 27% slices, 64% DSPs, and 70% block RAMs compared with the conventional method.
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spelling doaj.art-c2f287b95e4b49819b4f28421c9013172023-11-24T14:41:02ZengMDPI AGEntropy1099-43002023-11-012511153010.3390/e25111530Design and Implementation of a Low-Complexity Multi-<i>h</i> CPM Receiver with Linear Phase Approximation Synchronization AlgorithmLe Wang0Huan Wen1Xucen Wu2Qingping Song3School of Information Science and Technology, North China University of Technology, Beijing 100144, ChinaSchool of Information Science and Technology, North China University of Technology, Beijing 100144, ChinaSchool of Information Science and Technology, North China University of Technology, Beijing 100144, ChinaBeijing Institute of Control and Electronic Technology, Beijing 100038, ChinaMulti-<i>h</i> continuous phase modulation (CPM), with extremely high spectral efficiency, involves the plague of high demodulation complexity with a large number of matched filters and a complex trellis. In this paper, an efficient all-digital demodulator for multi-<i>h</i> continuous phase modulation (CPM) is proposed based on a low-complexity decision-directed synchronization algorithm. Based on the maximum-likelihood estimation of the carrier phase and timing errors, we propose a reduced-complexity timing error detector with linear phase approximation (LPA) to the phase of the multi-<i>h</i> CPM. Compared with the traditional synchronization methods, it avoids derivative matched filtering and reduces about 2/3 of matched filters. The estimated accuracy and bit error rate (BER) performance of the LPA-based synchronization algorithm have no loss, as shown by the numerical simulation. Its stability is verified by the derived S-curve. Then, the receivers with the LPA-based synchronization for the three kinds of promising multi-<i>h</i> CPM are implemented on a Xilinx Kintex-7 FPGA platform. The experimental results show that the onboard tested BER of the proposed design has an ignorable loss in the numerical simulation. The implementation overhead on FPGA is significantly reduced by about 27% slices, 64% DSPs, and 70% block RAMs compared with the conventional method.https://www.mdpi.com/1099-4300/25/11/1530multi-h CPMlinear phase approximation (LPA)synchronizationFPGA implementation
spellingShingle Le Wang
Huan Wen
Xucen Wu
Qingping Song
Design and Implementation of a Low-Complexity Multi-<i>h</i> CPM Receiver with Linear Phase Approximation Synchronization Algorithm
Entropy
multi-h CPM
linear phase approximation (LPA)
synchronization
FPGA implementation
title Design and Implementation of a Low-Complexity Multi-<i>h</i> CPM Receiver with Linear Phase Approximation Synchronization Algorithm
title_full Design and Implementation of a Low-Complexity Multi-<i>h</i> CPM Receiver with Linear Phase Approximation Synchronization Algorithm
title_fullStr Design and Implementation of a Low-Complexity Multi-<i>h</i> CPM Receiver with Linear Phase Approximation Synchronization Algorithm
title_full_unstemmed Design and Implementation of a Low-Complexity Multi-<i>h</i> CPM Receiver with Linear Phase Approximation Synchronization Algorithm
title_short Design and Implementation of a Low-Complexity Multi-<i>h</i> CPM Receiver with Linear Phase Approximation Synchronization Algorithm
title_sort design and implementation of a low complexity multi i h i cpm receiver with linear phase approximation synchronization algorithm
topic multi-h CPM
linear phase approximation (LPA)
synchronization
FPGA implementation
url https://www.mdpi.com/1099-4300/25/11/1530
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