Transverse Scaling of Schottky Barrier Charge-Trapping Cells for Energy-Efficient Applications
This work numerically elucidates the effects of transverse scaling on Schottky barrier charge-trapping cells for energy-efficient applications. Together with the scaled gate structures and charge-trapping dielectrics, variations in bias conditions on source-side injection are considered for properly...
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MDPI AG
2020-11-01
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Series: | Crystals |
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Online Access: | https://www.mdpi.com/2073-4352/10/11/1036 |
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author | Hung-Jin Teng Yu-Hsuan Chen Jr-Jie Tsai Nguyen Dang Chien Chenhsin Lien Chun-Hsing Shih |
author_facet | Hung-Jin Teng Yu-Hsuan Chen Jr-Jie Tsai Nguyen Dang Chien Chenhsin Lien Chun-Hsing Shih |
author_sort | Hung-Jin Teng |
collection | DOAJ |
description | This work numerically elucidates the effects of transverse scaling on Schottky barrier charge-trapping cells for energy-efficient applications. Together with the scaled gate structures and charge-trapping dielectrics, variations in bias conditions on source-side injection are considered for properly operating Schottky barrier cells in low-power or high-efficiency applications. A gate voltage of 5 to 9 V with a drain voltage of 1 to 3 V was employed to program the Schottky barrier cells. Both the non-planar double-gate gate structure and scaled dielectric layers effectively improve the source-side programming. When the gate voltage of 5 V was operated, there were roughly two orders of magnitude greater injected gate currents observed in the ONO-scaled double-gate cells. Five successive programming-trapping iterations were employed to consider the coupling of trapped charges and Schottky barriers, examining the differences in physical mechanisms between different design options. The gate structures, dielectric layers, and gate/drain voltages are key factors in designing transverse scaled Schottky barrier charge-trapping cells for low-power and high-efficiency applications. |
first_indexed | 2024-03-10T14:53:11Z |
format | Article |
id | doaj.art-c2ff0110919d45f0bbb379a382e8b427 |
institution | Directory Open Access Journal |
issn | 2073-4352 |
language | English |
last_indexed | 2024-03-10T14:53:11Z |
publishDate | 2020-11-01 |
publisher | MDPI AG |
record_format | Article |
series | Crystals |
spelling | doaj.art-c2ff0110919d45f0bbb379a382e8b4272023-11-20T20:52:16ZengMDPI AGCrystals2073-43522020-11-011011103610.3390/cryst10111036Transverse Scaling of Schottky Barrier Charge-Trapping Cells for Energy-Efficient ApplicationsHung-Jin Teng0Yu-Hsuan Chen1Jr-Jie Tsai2Nguyen Dang Chien3Chenhsin Lien4Chun-Hsing Shih5Department of Electrical Engineering, National Chi Nan University, Nantou 54561, TaiwanDepartment of Electrical Engineering, National Chi Nan University, Nantou 54561, TaiwanDepartment of Electrical Engineering, National Chi Nan University, Nantou 54561, TaiwanFaculty of Physics & Nuclear Engineering, Dalat University, Lam Dong 670000, VietnamInstitute of Electronics Engineering, National Tsing Hua University, Hsinchu 30013, TaiwanDepartment of Electrical Engineering, National Chi Nan University, Nantou 54561, TaiwanThis work numerically elucidates the effects of transverse scaling on Schottky barrier charge-trapping cells for energy-efficient applications. Together with the scaled gate structures and charge-trapping dielectrics, variations in bias conditions on source-side injection are considered for properly operating Schottky barrier cells in low-power or high-efficiency applications. A gate voltage of 5 to 9 V with a drain voltage of 1 to 3 V was employed to program the Schottky barrier cells. Both the non-planar double-gate gate structure and scaled dielectric layers effectively improve the source-side programming. When the gate voltage of 5 V was operated, there were roughly two orders of magnitude greater injected gate currents observed in the ONO-scaled double-gate cells. Five successive programming-trapping iterations were employed to consider the coupling of trapped charges and Schottky barriers, examining the differences in physical mechanisms between different design options. The gate structures, dielectric layers, and gate/drain voltages are key factors in designing transverse scaled Schottky barrier charge-trapping cells for low-power and high-efficiency applications.https://www.mdpi.com/2073-4352/10/11/1036Schottky barriersource-side injectioncharge-trapping memoryenergy-efficientnon-planar double-gatehigh-k dielectrics |
spellingShingle | Hung-Jin Teng Yu-Hsuan Chen Jr-Jie Tsai Nguyen Dang Chien Chenhsin Lien Chun-Hsing Shih Transverse Scaling of Schottky Barrier Charge-Trapping Cells for Energy-Efficient Applications Crystals Schottky barrier source-side injection charge-trapping memory energy-efficient non-planar double-gate high-k dielectrics |
title | Transverse Scaling of Schottky Barrier Charge-Trapping Cells for Energy-Efficient Applications |
title_full | Transverse Scaling of Schottky Barrier Charge-Trapping Cells for Energy-Efficient Applications |
title_fullStr | Transverse Scaling of Schottky Barrier Charge-Trapping Cells for Energy-Efficient Applications |
title_full_unstemmed | Transverse Scaling of Schottky Barrier Charge-Trapping Cells for Energy-Efficient Applications |
title_short | Transverse Scaling of Schottky Barrier Charge-Trapping Cells for Energy-Efficient Applications |
title_sort | transverse scaling of schottky barrier charge trapping cells for energy efficient applications |
topic | Schottky barrier source-side injection charge-trapping memory energy-efficient non-planar double-gate high-k dielectrics |
url | https://www.mdpi.com/2073-4352/10/11/1036 |
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