An Efficient Multi-Lane SpaceFibre Core for Spacecraft Data-Handling Networks

As one of the key technologies in spacecraft data-handling networks mounting high-resolution payloads, the multi-lane native SpaceFibre standard is designed to meet the demands for the high-speed and reliable interconnections between satellite payloads. A few studies are about the implementations of...

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Main Authors: Jingya Zheng, Junshe An, Yuanyuan Jiang
Format: Article
Language:English
Published: MDPI AG 2022-04-01
Series:Electronics
Subjects:
Online Access:https://www.mdpi.com/2079-9292/11/9/1410
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author Jingya Zheng
Junshe An
Yuanyuan Jiang
author_facet Jingya Zheng
Junshe An
Yuanyuan Jiang
author_sort Jingya Zheng
collection DOAJ
description As one of the key technologies in spacecraft data-handling networks mounting high-resolution payloads, the multi-lane native SpaceFibre standard is designed to meet the demands for the high-speed and reliable interconnections between satellite payloads. A few studies are about the implementations of a multi-lane SpaceFibre core. Even though they exhibit good performance, several limitations still, more or less, exist. We detail an efficient multi-lane SpaceFibre (E-ML-SpFi) core for high-rate and fault-tolerant data communication. The E-ML-SpFi core exploits a hierarchical method to decouple the complex control logic of the retransmission mechanism. The core employs a modified word re-ordering block to map an extended set of words on a real-time variable number of data-sending lanes. Meanwhile, the core introduces the architecture of a fast alignment subsystem to accelerate the alignment process. A hardware implementation on XC7Z100 FPGA shows that the E-ML-SpFi core has complete functionality stipulated by the standard and requires limited resources, with 6290 (2.26%) LUTs and 8252 (1.49%) FFs. The maximum operating frequency of the core is 200 MHz. Moreover, the recovery time is reduced up to 30.9% compared with previous work. Therefore, the core provides a valid solution for future interconnection networks onboard spacecraft.
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spelling doaj.art-c3254e9b81cd48bd8183735b86f1f6642023-11-23T08:03:13ZengMDPI AGElectronics2079-92922022-04-01119141010.3390/electronics11091410An Efficient Multi-Lane SpaceFibre Core for Spacecraft Data-Handling NetworksJingya Zheng0Junshe An1Yuanyuan Jiang2Key Laboratory of Electronics and Information Technology for Space Systems, National Space Science Center, Chinese Academy of Sciences, Beijing 100190, ChinaKey Laboratory of Electronics and Information Technology for Space Systems, National Space Science Center, Chinese Academy of Sciences, Beijing 100190, ChinaKey Laboratory of Electronics and Information Technology for Space Systems, National Space Science Center, Chinese Academy of Sciences, Beijing 100190, ChinaAs one of the key technologies in spacecraft data-handling networks mounting high-resolution payloads, the multi-lane native SpaceFibre standard is designed to meet the demands for the high-speed and reliable interconnections between satellite payloads. A few studies are about the implementations of a multi-lane SpaceFibre core. Even though they exhibit good performance, several limitations still, more or less, exist. We detail an efficient multi-lane SpaceFibre (E-ML-SpFi) core for high-rate and fault-tolerant data communication. The E-ML-SpFi core exploits a hierarchical method to decouple the complex control logic of the retransmission mechanism. The core employs a modified word re-ordering block to map an extended set of words on a real-time variable number of data-sending lanes. Meanwhile, the core introduces the architecture of a fast alignment subsystem to accelerate the alignment process. A hardware implementation on XC7Z100 FPGA shows that the E-ML-SpFi core has complete functionality stipulated by the standard and requires limited resources, with 6290 (2.26%) LUTs and 8252 (1.49%) FFs. The maximum operating frequency of the core is 200 MHz. Moreover, the recovery time is reduced up to 30.9% compared with previous work. Therefore, the core provides a valid solution for future interconnection networks onboard spacecraft.https://www.mdpi.com/2079-9292/11/9/1410SpaceFibremulti-lanefault-tolerant controlhardware architecturesystem on chipFPGAs
spellingShingle Jingya Zheng
Junshe An
Yuanyuan Jiang
An Efficient Multi-Lane SpaceFibre Core for Spacecraft Data-Handling Networks
Electronics
SpaceFibre
multi-lane
fault-tolerant control
hardware architecture
system on chip
FPGAs
title An Efficient Multi-Lane SpaceFibre Core for Spacecraft Data-Handling Networks
title_full An Efficient Multi-Lane SpaceFibre Core for Spacecraft Data-Handling Networks
title_fullStr An Efficient Multi-Lane SpaceFibre Core for Spacecraft Data-Handling Networks
title_full_unstemmed An Efficient Multi-Lane SpaceFibre Core for Spacecraft Data-Handling Networks
title_short An Efficient Multi-Lane SpaceFibre Core for Spacecraft Data-Handling Networks
title_sort efficient multi lane spacefibre core for spacecraft data handling networks
topic SpaceFibre
multi-lane
fault-tolerant control
hardware architecture
system on chip
FPGAs
url https://www.mdpi.com/2079-9292/11/9/1410
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