| Summary: | This manuscript includes the design and evaluation of the new four 16×16 S-boxes for subbyte operation in image encryption applications and estimates their strength using the following parameters: Dynamic Distance, BIC non-linearity, Bijective, Non-linearity, Strict Avalanche Criterion (SAC), and Balanced criterion. The S-box matrix is designed by a new reconfigurable 3D-Chaotic PRNG. This PRNG is designed using four different 3D chaotic systems i.e. Lorenz, Chen, Lu, and Pehlivan's chaotic systems. This reconfigurable architecture of PRNG exploits the ODEs of these four attractors that fit all four chaotic systems in a single circuit. The first part of this manuscript is focused to develop hardware-efficient VLSI architecture. To demonstrate the hardware performance, the PRNG circuit is implemented in Virtex-5 (XC5VLX50T) FPGA. A performance comparison of proposed and existing PRNGs (in terms of timing performance, area constraint, power dissipation and statistical testing) has been presented in this work. The PRNG generates the 24-bit random number at 96.438-MHz. The area of FPGA is occupied by only 16.66 %, 1.08%, 0.33%, and 1.15% of the available DSP blocks, slice LUTs, slice registers and slices respectively. The designed S-boxes using reconfigurable PRNG fulfill the following criteria: Dynamic Distance, BIC non-linearity, Bijective, Non-linearity, Strict Avalanche Criterion (SAC), and Balanced criterion.
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