Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies
Bit-serial multiply-accumulate units (MACs) play a crucial role in various hardware accelerator applications, including deep learning, image processing, and signal processing. Despite the advantages of bit-serial MACs, such as a small footprint, full hardware utilization, and high frequency, their s...
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MDPI AG
2023-05-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/12/10/2177 |
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| author | Xiaoshu Cheng Yiwen Wang Jiazhi Liu Weiran Ding Hongfei Lou Ping Li |
| author_facet | Xiaoshu Cheng Yiwen Wang Jiazhi Liu Weiran Ding Hongfei Lou Ping Li |
| author_sort | Xiaoshu Cheng |
| collection | DOAJ |
| description | Bit-serial multiply-accumulate units (MACs) play a crucial role in various hardware accelerator applications, including deep learning, image processing, and signal processing. Despite the advantages of bit-serial MACs, such as a small footprint, full hardware utilization, and high frequency, their serial nature can lead to high latency and potentially compromised performance. This study investigates the potential of bit-serial solutions by applying Booth encoding to bit-serial multipliers within MACs to enhance area and power efficiencies. We present two types of bit-serial MACs based on radix-2 and radix-4 Booth encoding multipliers, respectively. Their performance is assessed through simulations and synthesis results, demonstrating the benefits of the proposed approach. The radix-4 Booth bit-serial MAC improves power and area efficiencies compared to the original bit-serial MAC. Operating at TSMC 90 nm and 150 MHz, our design exhibits a remarkable 96.39% reduction in area-power-product (APP). Moreover, the prototype verification on a Xilinx Kintex-7 FPGA proved successful. The proposed solution offers significant advantages in energy efficiency, area reduction, and APP, making it a promising candidate for next-generation hardware accelerators in offline inference, low-power devices, and other applications. |
| first_indexed | 2024-03-11T03:48:05Z |
| format | Article |
| id | doaj.art-c58d8e19efea4930876b6c3bc5aca2d5 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-11T03:48:05Z |
| publishDate | 2023-05-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-c58d8e19efea4930876b6c3bc5aca2d52023-11-18T01:08:44ZengMDPI AGElectronics2079-92922023-05-011210217710.3390/electronics12102177Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy EfficienciesXiaoshu Cheng0Yiwen Wang1Jiazhi Liu2Weiran Ding3Hongfei Lou4Ping Li5School of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu 610054, ChinaSchool of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu 610054, ChinaSchool of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu 610054, ChinaSchool of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu 610054, ChinaSchool of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu 610054, ChinaSchool of Integrated Circuit Science and Engineering, University of Electronic Science and Technology of China, Chengdu 610054, ChinaBit-serial multiply-accumulate units (MACs) play a crucial role in various hardware accelerator applications, including deep learning, image processing, and signal processing. Despite the advantages of bit-serial MACs, such as a small footprint, full hardware utilization, and high frequency, their serial nature can lead to high latency and potentially compromised performance. This study investigates the potential of bit-serial solutions by applying Booth encoding to bit-serial multipliers within MACs to enhance area and power efficiencies. We present two types of bit-serial MACs based on radix-2 and radix-4 Booth encoding multipliers, respectively. Their performance is assessed through simulations and synthesis results, demonstrating the benefits of the proposed approach. The radix-4 Booth bit-serial MAC improves power and area efficiencies compared to the original bit-serial MAC. Operating at TSMC 90 nm and 150 MHz, our design exhibits a remarkable 96.39% reduction in area-power-product (APP). Moreover, the prototype verification on a Xilinx Kintex-7 FPGA proved successful. The proposed solution offers significant advantages in energy efficiency, area reduction, and APP, making it a promising candidate for next-generation hardware accelerators in offline inference, low-power devices, and other applications.https://www.mdpi.com/2079-9292/12/10/2177hardware acceleratorBooth encodingbit-serialmultipliermultiply-accumulate unit (MAC) |
| spellingShingle | Xiaoshu Cheng Yiwen Wang Jiazhi Liu Weiran Ding Hongfei Lou Ping Li Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies Electronics hardware accelerator Booth encoding bit-serial multiplier multiply-accumulate unit (MAC) |
| title | Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies |
| title_full | Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies |
| title_fullStr | Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies |
| title_full_unstemmed | Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies |
| title_short | Booth Encoded Bit-Serial Multiply-Accumulate Units with Improved Area and Energy Efficiencies |
| title_sort | booth encoded bit serial multiply accumulate units with improved area and energy efficiencies |
| topic | hardware accelerator Booth encoding bit-serial multiplier multiply-accumulate unit (MAC) |
| url | https://www.mdpi.com/2079-9292/12/10/2177 |
| work_keys_str_mv | AT xiaoshucheng boothencodedbitserialmultiplyaccumulateunitswithimprovedareaandenergyefficiencies AT yiwenwang boothencodedbitserialmultiplyaccumulateunitswithimprovedareaandenergyefficiencies AT jiazhiliu boothencodedbitserialmultiplyaccumulateunitswithimprovedareaandenergyefficiencies AT weiranding boothencodedbitserialmultiplyaccumulateunitswithimprovedareaandenergyefficiencies AT hongfeilou boothencodedbitserialmultiplyaccumulateunitswithimprovedareaandenergyefficiencies AT pingli boothencodedbitserialmultiplyaccumulateunitswithimprovedareaandenergyefficiencies |