Efficient <em>k</em>-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning
A novel <em>k</em>-winners-take-all (<em>k</em>-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing <em>k</em&...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
MDPI AG
2012-08-01
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| Series: | Sensors |
| Subjects: | |
| Online Access: | http://www.mdpi.com/1424-8220/12/9/11661 |
| _version_ | 1798041424475717632 |
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| author | Wen-Jyi Hwang Hui-Ya Li Chien-Min Ou |
| author_facet | Wen-Jyi Hwang Hui-Ya Li Chien-Min Ou |
| author_sort | Wen-Jyi Hwang |
| collection | DOAJ |
| description | A novel <em>k</em>-winners-take-all (<em>k</em>-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing <em>k</em>-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other <em>k</em>-WTA CL counterparts operating with or without hardware support. |
| first_indexed | 2024-04-11T22:21:20Z |
| format | Article |
| id | doaj.art-c5a10aed788a4fdbad7309d446a2909b |
| institution | Directory Open Access Journal |
| issn | 1424-8220 |
| language | English |
| last_indexed | 2024-04-11T22:21:20Z |
| publishDate | 2012-08-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Sensors |
| spelling | doaj.art-c5a10aed788a4fdbad7309d446a2909b2022-12-22T04:00:06ZengMDPI AGSensors1424-82202012-08-01129116611168310.3390/s120911661Efficient <em>k</em>-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip LearningWen-Jyi HwangHui-Ya LiChien-Min OuA novel <em>k</em>-winners-take-all (<em>k</em>-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing <em>k</em>-WTA competition processes associated with different training vectors to be performed concurrently. The pipeline architecture employs a novel codeword swapping scheme so that neurons failing the competition for a training vector are immediately available for the competitions for the subsequent training vectors. The architecture is implemented by the field programmable gate array (FPGA). It is used as a hardware accelerator in a system on programmable chip (SOPC) for realtime on-chip learning. Experimental results show that the SOPC has significantly lower training time than that of other <em>k</em>-WTA CL counterparts operating with or without hardware support.http://www.mdpi.com/1424-8220/12/9/11661reconfigurable computingsystem on programmable chipFPGAcompetitive learning<em>k</em>-winners-take-all |
| spellingShingle | Wen-Jyi Hwang Hui-Ya Li Chien-Min Ou Efficient <em>k</em>-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning Sensors reconfigurable computing system on programmable chip FPGA competitive learning <em>k</em>-winners-take-all |
| title | Efficient <em>k</em>-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning |
| title_full | Efficient <em>k</em>-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning |
| title_fullStr | Efficient <em>k</em>-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning |
| title_full_unstemmed | Efficient <em>k</em>-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning |
| title_short | Efficient <em>k</em>-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning |
| title_sort | efficient lt em gt k lt em gt winner take all competitive learning hardware architecture for on chip learning |
| topic | reconfigurable computing system on programmable chip FPGA competitive learning <em>k</em>-winners-take-all |
| url | http://www.mdpi.com/1424-8220/12/9/11661 |
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