Efficient <em>k</em>-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

Efficient <em>k</em>-Winner-Take-All Competitive Learning Hardware Architecture for On-Chip Learning

A novel <em>k</em>-winners-take-all (<em>k</em>-WTA) competitive learning (CL) hardware architecture is presented for on-chip learning in this paper. The architecture is based on an efficient pipeline allowing <em>k</em&...

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Bibliographic Details
Main Authors: Wen-Jyi Hwang, Hui-Ya Li, Chien-Min Ou
Format: Article
Language:English
Published: MDPI AG 2012-08-01
Series:Sensors
Subjects:
reconfigurable computing
system on programmable chip
FPGA
competitive learning
<em>k</em>-winners-take-all
Online Access:http://www.mdpi.com/1424-8220/12/9/11661

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