VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC
Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integ...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-04-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/8/899 |
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| author | Bushra Sultana Anees Ullah Arsalan Ali Malik Ali Zahir Pedro Reviriego Fahad Bin Muslim Nasim Ullah Waleed Ahmad |
| author_facet | Bushra Sultana Anees Ullah Arsalan Ali Malik Ali Zahir Pedro Reviriego Fahad Bin Muslim Nasim Ullah Waleed Ahmad |
| author_sort | Bushra Sultana |
| collection | DOAJ |
| description | Hybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches. |
| first_indexed | 2024-03-10T12:28:21Z |
| format | Article |
| id | doaj.art-c64db0d77fc54ffebcb3a44197aa2803 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T12:28:21Z |
| publishDate | 2021-04-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-c64db0d77fc54ffebcb3a44197aa28032023-11-21T14:53:20ZengMDPI AGElectronics2079-92922021-04-0110889910.3390/electronics10080899VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOCBushra Sultana0Anees Ullah1Arsalan Ali Malik2Ali Zahir3Pedro Reviriego4Fahad Bin Muslim5Nasim Ullah6Waleed Ahmad7Department of Electrical and Computer Engineering, Sir Syed CASE Institute of Technology, Islamabad 44000, PakistanDepartment of Electronics Engineering, Abbottabad Campus, University of Engineering and Technology, Peshawar, Abbottabad 22010, PakistanDepartment of Electrical and Computer Engineering, Sir Syed CASE Institute of Technology, Islamabad 44000, PakistanDepartment of Electrical and Computer Engineering, Abbottabad Campus, COMSATS University Islamabad, Abbottabad 22010, PakistanDepartment of Telematic Engineering, Universidad Carlos III of Madrid, Leganés, 28911 Madrid, SpainDepartment of Electronics Engineering, Iqra University, Islamabad 75500, PakistanDepartment of Electrical Engineering, College of Engineering, Taif University, Taif 11099, Saudi ArabiaDepartment of Electrical and Computer Engineering, University of Poonch, Rawalakot 12350, PakistanHybrid architectures integrating a processor with an SRAM-based FPGA fabric—for example, Xilinx ZynQ SoC—are increasingly being used as a single-chip solution in several market segments to replace multi-chip designs. These devices not only provide advantages in terms of logic density, cost and integration, but also provide run-time in-field reconfiguration capabilities. However, the current reconfiguration capabilities provided by vendor tools are limited to the module level. Therefore, incremental run-time configuration memory changes require a lengthy compilation time for off-line bitstream generation along with storage and reconfiguration time overheads with traditional vendor methodologies. In this paper, an internal configuration access port (ICAP) controller that provides a versatile fine-grain resource-level incremental reconfiguration of the programmable logic (PL) resources in ZynQ SoC is presented. The proposed controller implemented in PL, called VR-ZyCAP, can reconfigure look-up tables (LUTs) and Flip-Flops (FF). The run-time reconfiguration of FF is achieved through a reset after reconfiguration (RAR)-featured partial bitstream to avoid the unintended state corruption of other memory elements. Along with versatility, our proposed controller improves the reconfiguration time by 30 times for FFs compared to state-of-the-art works while achieving a nearly 400-fold increase in speed for LUTs when compared to vendor-supported software approaches. In addition, it achieves competitive resource utilization when compared to existing approaches.https://www.mdpi.com/2079-9292/10/8/899run-time reconfigurationICAP controllersZynQ SoCs |
| spellingShingle | Bushra Sultana Anees Ullah Arsalan Ali Malik Ali Zahir Pedro Reviriego Fahad Bin Muslim Nasim Ullah Waleed Ahmad VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC Electronics run-time reconfiguration ICAP controllers ZynQ SoCs |
| title | VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC |
| title_full | VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC |
| title_fullStr | VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC |
| title_full_unstemmed | VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC |
| title_short | VR-ZYCAP: A Versatile Resourse-Level ICAP Controller for ZYNQ SOC |
| title_sort | vr zycap a versatile resourse level icap controller for zynq soc |
| topic | run-time reconfiguration ICAP controllers ZynQ SoCs |
| url | https://www.mdpi.com/2079-9292/10/8/899 |
| work_keys_str_mv | AT bushrasultana vrzycapaversatileresourselevelicapcontrollerforzynqsoc AT aneesullah vrzycapaversatileresourselevelicapcontrollerforzynqsoc AT arsalanalimalik vrzycapaversatileresourselevelicapcontrollerforzynqsoc AT alizahir vrzycapaversatileresourselevelicapcontrollerforzynqsoc AT pedroreviriego vrzycapaversatileresourselevelicapcontrollerforzynqsoc AT fahadbinmuslim vrzycapaversatileresourselevelicapcontrollerforzynqsoc AT nasimullah vrzycapaversatileresourselevelicapcontrollerforzynqsoc AT waleedahmad vrzycapaversatileresourselevelicapcontrollerforzynqsoc |