Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache Attacks
Cache attacks exploit the hardware vulnerabilities inherent to modern processors and pose a new threat to Internet of Things (IoT) devices. Intuitively, different cache parameter configurations directly impact the attack effectiveness, but the current research on this issue is not systematic or comp...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2022-07-01
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| Series: | Electronics |
| Subjects: | |
| Online Access: | https://www.mdpi.com/2079-9292/11/15/2340 |
| _version_ | 1797442464742637568 |
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| author | Pengfei Guo Yingjian Yan Bin Ye Chunsheng Zhu Lichao Zhang Ting Shen Lin Chen |
| author_facet | Pengfei Guo Yingjian Yan Bin Ye Chunsheng Zhu Lichao Zhang Ting Shen Lin Chen |
| author_sort | Pengfei Guo |
| collection | DOAJ |
| description | Cache attacks exploit the hardware vulnerabilities inherent to modern processors and pose a new threat to Internet of Things (IoT) devices. Intuitively, different cache parameter configurations directly impact the attack effectiveness, but the current research on this issue is not systematic or comprehensive enough. This paper’s primary focus is to evaluate how different cache parameter configurations affect access-driven attacks. We build a flexible and configurable simulation verification environment based on the Chipyard framework. To reduce the interference of other factors, we established a baseline for each category of parameter evaluation. We propose a novel evaluation model, called Key Score Scissors Differential (KSSD), for evaluating common private and shared cache parameters under the local and cross-core attack models, respectively; among these are private cache replacement policy, private cache capacity, cache line size, private cache associativity, shared cache capacity, and shared cache associativity. Ours is the first evaluation of the shared cache under a cross-core attack model. As a result of the evaluation, the quantitative metrics can provide a reliable indication of information leakage level under the current cache configuration, which is helpful for attackers, defenders, and evaluators. Furthermore, we provide detailed explanations and discussions of inconsistent findings by comparing our results with the existing literature. |
| first_indexed | 2024-03-09T12:42:13Z |
| format | Article |
| id | doaj.art-c6544a174bd14983853e66981e9ca7f6 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-09T12:42:13Z |
| publishDate | 2022-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-c6544a174bd14983853e66981e9ca7f62023-11-30T22:17:09ZengMDPI AGElectronics2079-92922022-07-011115234010.3390/electronics11152340Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache AttacksPengfei Guo0Yingjian Yan1Bin Ye2Chunsheng Zhu3Lichao Zhang4Ting Shen5Lin Chen6College of Cryptography Engineering, Information Engineering University, Zhengzhou 450001, ChinaCollege of Cryptography Engineering, Information Engineering University, Zhengzhou 450001, ChinaState Grid Ningbo Electric Power Supply Company, Ningbo 315000, ChinaCollege of Cryptography Engineering, Information Engineering University, Zhengzhou 450001, ChinaCollege of Cryptography Engineering, Information Engineering University, Zhengzhou 450001, ChinaZhejiang Dongan Testing Technology Co., Ltd., Hangzhou 310012, ChinaCollege of Cryptography Engineering, Information Engineering University, Zhengzhou 450001, ChinaCache attacks exploit the hardware vulnerabilities inherent to modern processors and pose a new threat to Internet of Things (IoT) devices. Intuitively, different cache parameter configurations directly impact the attack effectiveness, but the current research on this issue is not systematic or comprehensive enough. This paper’s primary focus is to evaluate how different cache parameter configurations affect access-driven attacks. We build a flexible and configurable simulation verification environment based on the Chipyard framework. To reduce the interference of other factors, we established a baseline for each category of parameter evaluation. We propose a novel evaluation model, called Key Score Scissors Differential (KSSD), for evaluating common private and shared cache parameters under the local and cross-core attack models, respectively; among these are private cache replacement policy, private cache capacity, cache line size, private cache associativity, shared cache capacity, and shared cache associativity. Ours is the first evaluation of the shared cache under a cross-core attack model. As a result of the evaluation, the quantitative metrics can provide a reliable indication of information leakage level under the current cache configuration, which is helpful for attackers, defenders, and evaluators. Furthermore, we provide detailed explanations and discussions of inconsistent findings by comparing our results with the existing literature.https://www.mdpi.com/2079-9292/11/15/2340cache parametersevaluationaccess-driven cache attacksAESRISC-VChipyard |
| spellingShingle | Pengfei Guo Yingjian Yan Bin Ye Chunsheng Zhu Lichao Zhang Ting Shen Lin Chen Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache Attacks Electronics cache parameters evaluation access-driven cache attacks AES RISC-V Chipyard |
| title | Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache Attacks |
| title_full | Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache Attacks |
| title_fullStr | Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache Attacks |
| title_full_unstemmed | Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache Attacks |
| title_short | Evaluation on the Impact of Cache Parameter Selection in Access-Driven Cache Attacks |
| title_sort | evaluation on the impact of cache parameter selection in access driven cache attacks |
| topic | cache parameters evaluation access-driven cache attacks AES RISC-V Chipyard |
| url | https://www.mdpi.com/2079-9292/11/15/2340 |
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