Optimized design and performance analysis of novel comparator and full adder in nanoscale
In a vastly rapid progress of very large scale integration (VLSI) archetype, it is the requirement of moment to attain a consistent model with swifter functioning speed and low power utilization. Quantum-dot Cellular Automata (QCA) is an inimitable transistorless computation approach that is based o...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Taylor & Francis Group
2016-12-01
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| Series: | Cogent Engineering |
| Subjects: | |
| Online Access: | http://dx.doi.org/10.1080/23311916.2016.1237864 |
| _version_ | 1797719528482799616 |
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| author | Md. Abdullah-Al-Shafi Ali Newaz Bahar |
| author_facet | Md. Abdullah-Al-Shafi Ali Newaz Bahar |
| author_sort | Md. Abdullah-Al-Shafi |
| collection | DOAJ |
| description | In a vastly rapid progress of very large scale integration (VLSI) archetype, it is the requirement of moment to attain a consistent model with swifter functioning speed and low power utilization. Quantum-dot Cellular Automata (QCA) is an inimitable transistorless computation approach that is based on semiconductor substantial and a substitute for customary CMOS and VLSI archetype at nanoscale point which comprises a better switching frequency, enhanced scale integration and small extent. In the design of digital logic, a comparator is the essential forming component which implements the resemblance of two numbers and a binary full adder is a major entity in digital logic systems. This paper deals with an expanded layout of reversible 1-bit comparator and proficient full adder without wire-crossing in QCA. The proposed layouts are significantly declined in terms of area and cell complexity, assessed to other layouts and clock cycle is retained at least. Quantum costs of the proposed circuits are estimated and compared, that shows the proposed QCA layouts have lesser quantum cost equated to regular designs and the energy depletion by the circuits endorses the view of QCA nano-circuit attending as a substitute level for the completion of reversible computing. Under thermal unpredictability, the constancy of the proposed designs is evaluated which show the operating efficacy of the designs. The simulation outcomes in QCADesigner tool approve that the presented designs performs properly and can be operated as an extreme performing design in QCA technology. |
| first_indexed | 2024-03-12T09:07:16Z |
| format | Article |
| id | doaj.art-c8d9a65c6e454bc6a484ca7dd14bc99f |
| institution | Directory Open Access Journal |
| issn | 2331-1916 |
| language | English |
| last_indexed | 2024-03-12T09:07:16Z |
| publishDate | 2016-12-01 |
| publisher | Taylor & Francis Group |
| record_format | Article |
| series | Cogent Engineering |
| spelling | doaj.art-c8d9a65c6e454bc6a484ca7dd14bc99f2023-09-02T15:17:03ZengTaylor & Francis GroupCogent Engineering2331-19162016-12-013110.1080/23311916.2016.12378641237864Optimized design and performance analysis of novel comparator and full adder in nanoscaleMd. Abdullah-Al-Shafi0Ali Newaz Bahar1University of DhakaMawlana Bhashani Science & Technology UniversityIn a vastly rapid progress of very large scale integration (VLSI) archetype, it is the requirement of moment to attain a consistent model with swifter functioning speed and low power utilization. Quantum-dot Cellular Automata (QCA) is an inimitable transistorless computation approach that is based on semiconductor substantial and a substitute for customary CMOS and VLSI archetype at nanoscale point which comprises a better switching frequency, enhanced scale integration and small extent. In the design of digital logic, a comparator is the essential forming component which implements the resemblance of two numbers and a binary full adder is a major entity in digital logic systems. This paper deals with an expanded layout of reversible 1-bit comparator and proficient full adder without wire-crossing in QCA. The proposed layouts are significantly declined in terms of area and cell complexity, assessed to other layouts and clock cycle is retained at least. Quantum costs of the proposed circuits are estimated and compared, that shows the proposed QCA layouts have lesser quantum cost equated to regular designs and the energy depletion by the circuits endorses the view of QCA nano-circuit attending as a substitute level for the completion of reversible computing. Under thermal unpredictability, the constancy of the proposed designs is evaluated which show the operating efficacy of the designs. The simulation outcomes in QCADesigner tool approve that the presented designs performs properly and can be operated as an extreme performing design in QCA technology.http://dx.doi.org/10.1080/23311916.2016.1237864quantum cellular automatacomparatorbinary full adderpower consumption |
| spellingShingle | Md. Abdullah-Al-Shafi Ali Newaz Bahar Optimized design and performance analysis of novel comparator and full adder in nanoscale Cogent Engineering quantum cellular automata comparator binary full adder power consumption |
| title | Optimized design and performance analysis of novel comparator and full adder in nanoscale |
| title_full | Optimized design and performance analysis of novel comparator and full adder in nanoscale |
| title_fullStr | Optimized design and performance analysis of novel comparator and full adder in nanoscale |
| title_full_unstemmed | Optimized design and performance analysis of novel comparator and full adder in nanoscale |
| title_short | Optimized design and performance analysis of novel comparator and full adder in nanoscale |
| title_sort | optimized design and performance analysis of novel comparator and full adder in nanoscale |
| topic | quantum cellular automata comparator binary full adder power consumption |
| url | http://dx.doi.org/10.1080/23311916.2016.1237864 |
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