| Summary: | Recent advances in very-large-scale integration (VLSI) technologies have offered the capability of integrating thousands of processing elements onto a single silicon microchip. Multiprocessor systems-on-chips (MPSoCs) are the latest creation of this technology evolution. As an interconnection network, Network-on-Chip (NoC) has emerged as a scalable and promising solution for MPSoCs to achieve high performance. In NoCs, a routing algorithm is a critical part of a router and provides a path for a packet toward its destination. Every routing algorithm should exhibit two characteristics. First, the route selection function should provide enough degree of adaptiveness to avoid network congestion. Second, it should not offer stale information on network congestion status to the neighboring routers. Many researchers have investigated network congestion and proposed techniques to control/avoid congestion. Such congestion avoidance-based algorithms significantly improve NoC performance. However, they may result in hardware overhead for side network implementation to collect congestion status. This paper reviews various output selection strategies used by routing algorithms to route a packet on a less congested network region. It also classifies them based on techniques adopted to handle and propagate congestion information. Additionally, this article provides the implementation and analysis details of state-of-art selection methods.
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