Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs
Recent advances in very-large-scale integration (VLSI) technologies have offered the capability of integrating thousands of processing elements onto a single silicon microchip. Multiprocessor systems-on-chips (MPSoCs) are the latest creation of this technology evolution. As an interconnection networ...
| Main Authors: | , , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2022-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9973301/ |
| _version_ | 1811293233202855936 |
|---|---|
| author | Rajendra Singh Manoj Kumar Bohra Prashant Hemrajani Anshuman Kalla Devershi Pallavi Bhatt Nitin Purohit Masoud Daneshtalab |
| author_facet | Rajendra Singh Manoj Kumar Bohra Prashant Hemrajani Anshuman Kalla Devershi Pallavi Bhatt Nitin Purohit Masoud Daneshtalab |
| author_sort | Rajendra Singh |
| collection | DOAJ |
| description | Recent advances in very-large-scale integration (VLSI) technologies have offered the capability of integrating thousands of processing elements onto a single silicon microchip. Multiprocessor systems-on-chips (MPSoCs) are the latest creation of this technology evolution. As an interconnection network, Network-on-Chip (NoC) has emerged as a scalable and promising solution for MPSoCs to achieve high performance. In NoCs, a routing algorithm is a critical part of a router and provides a path for a packet toward its destination. Every routing algorithm should exhibit two characteristics. First, the route selection function should provide enough degree of adaptiveness to avoid network congestion. Second, it should not offer stale information on network congestion status to the neighboring routers. Many researchers have investigated network congestion and proposed techniques to control/avoid congestion. Such congestion avoidance-based algorithms significantly improve NoC performance. However, they may result in hardware overhead for side network implementation to collect congestion status. This paper reviews various output selection strategies used by routing algorithms to route a packet on a less congested network region. It also classifies them based on techniques adopted to handle and propagate congestion information. Additionally, this article provides the implementation and analysis details of state-of-art selection methods. |
| first_indexed | 2024-04-13T04:58:22Z |
| format | Article |
| id | doaj.art-c8fe2e5784714af0aad196efd71ea0b8 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-13T04:58:22Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-c8fe2e5784714af0aad196efd71ea0b82022-12-22T03:01:25ZengIEEEIEEE Access2169-35362022-01-011012924512926810.1109/ACCESS.2022.32274609973301Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCsRajendra Singh0Manoj Kumar Bohra1Prashant Hemrajani2Anshuman Kalla3https://orcid.org/0000-0002-3985-4578Devershi Pallavi Bhatt4Nitin Purohit5https://orcid.org/0000-0002-9809-1988Masoud Daneshtalab6Department of Computer and Communication Engineering, Manipal University Jaipur, Jaipur, IndiaDepartment of Computer and Communication Engineering, Manipal University Jaipur, Jaipur, IndiaDepartment of Computer and Communication Engineering, Manipal University Jaipur, Jaipur, IndiaChhotubhai Gopalbhai Patel Institute of Technology (CGPIT), Uka Tarsadia University, Bardoli, Gujarat, IndiaDepartment of Computer Application, Manipal University Jaipur, Jaipur, IndiaDepartment of Computer Science, Kebri Dehar University, Kebri Dehar, EthiopiaMälardalen University, Västerås, SwedenRecent advances in very-large-scale integration (VLSI) technologies have offered the capability of integrating thousands of processing elements onto a single silicon microchip. Multiprocessor systems-on-chips (MPSoCs) are the latest creation of this technology evolution. As an interconnection network, Network-on-Chip (NoC) has emerged as a scalable and promising solution for MPSoCs to achieve high performance. In NoCs, a routing algorithm is a critical part of a router and provides a path for a packet toward its destination. Every routing algorithm should exhibit two characteristics. First, the route selection function should provide enough degree of adaptiveness to avoid network congestion. Second, it should not offer stale information on network congestion status to the neighboring routers. Many researchers have investigated network congestion and proposed techniques to control/avoid congestion. Such congestion avoidance-based algorithms significantly improve NoC performance. However, they may result in hardware overhead for side network implementation to collect congestion status. This paper reviews various output selection strategies used by routing algorithms to route a packet on a less congested network region. It also classifies them based on techniques adopted to handle and propagate congestion information. Additionally, this article provides the implementation and analysis details of state-of-art selection methods.https://ieeexplore.ieee.org/document/9973301/Network-on-chiprouting algorithmcongestionselection methodstraffic distribution |
| spellingShingle | Rajendra Singh Manoj Kumar Bohra Prashant Hemrajani Anshuman Kalla Devershi Pallavi Bhatt Nitin Purohit Masoud Daneshtalab Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs IEEE Access Network-on-chip routing algorithm congestion selection methods traffic distribution |
| title | Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs |
| title_full | Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs |
| title_fullStr | Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs |
| title_full_unstemmed | Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs |
| title_short | Review, Analysis, and Implementation of Path Selection Strategies for 2D NoCs |
| title_sort | review analysis and implementation of path selection strategies for 2d nocs |
| topic | Network-on-chip routing algorithm congestion selection methods traffic distribution |
| url | https://ieeexplore.ieee.org/document/9973301/ |
| work_keys_str_mv | AT rajendrasingh reviewanalysisandimplementationofpathselectionstrategiesfor2dnocs AT manojkumarbohra reviewanalysisandimplementationofpathselectionstrategiesfor2dnocs AT prashanthemrajani reviewanalysisandimplementationofpathselectionstrategiesfor2dnocs AT anshumankalla reviewanalysisandimplementationofpathselectionstrategiesfor2dnocs AT devershipallavibhatt reviewanalysisandimplementationofpathselectionstrategiesfor2dnocs AT nitinpurohit reviewanalysisandimplementationofpathselectionstrategiesfor2dnocs AT masouddaneshtalab reviewanalysisandimplementationofpathselectionstrategiesfor2dnocs |