On the Design of SSRS and RS Codes for Enhancing the Integrity of Information Storage in NAND Flash Memories
The revolution in the field of information processing systems has created a huge demand for reliable and enhanced data storage capabilities. This demand is being met by advances in channel coding algorithms along with upward scaling of the capacities of hardware devices. NAND Flash memory is a type...
| Main Authors: | , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2023-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10179920/ |
| _version_ | 1797772616214249472 |
|---|---|
| author | G. Achala U. Shripathi Acharya Pathipati Srihari |
| author_facet | G. Achala U. Shripathi Acharya Pathipati Srihari |
| author_sort | G. Achala |
| collection | DOAJ |
| description | The revolution in the field of information processing systems has created a huge demand for reliable and enhanced data storage capabilities. This demand is being met by advances in channel coding algorithms along with upward scaling of the capacities of hardware devices. NAND Flash memory is a type of non-volatile memory. Scaling of the size of flash memories from Single Level Cell (SLC) devices to Multilevel cell (MLC) devices has increased the storage capacity. However, these multi-bit per cell architectures are characterized by significantly higher Raw Bit Error Rate (RBER) values when compared with SLC architectures. The requirement of low Undetected Bit Error Rate (UBER) values has motivated us to synthesize powerful channel codes for enhancing the integrity of information Storage in multi-level NAND Flash Memory devices. This paper describes the synthesis of novel Subfield Subcodes of Reed Solomon Codes (SSRS) and Reed-Solomon (RS) codes which are matched to multi-bit per cell architectures. UBER values have been calculated for each of the synthesized codes described in this paper. This allows the determination of the performance and the improvement in data storage integrity brought by using these codes. We have shown that the synthesized SSRS and RS codes can provide very low UBER even when the corresponding RBER values are appreciable. As RS codes permit the detection and correction of a greater number of errors for a given code length, their performance is superior to that of SSRS codes. This improved performance is obtained at the cost of greater complexity of encoding and decoding processes. |
| first_indexed | 2024-03-12T21:54:30Z |
| format | Article |
| id | doaj.art-ca015754008b450aa23aaa748b6d1bc4 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-03-12T21:54:30Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-ca015754008b450aa23aaa748b6d1bc42023-07-25T23:00:27ZengIEEEIEEE Access2169-35362023-01-0111731987321710.1109/ACCESS.2023.329454410179920On the Design of SSRS and RS Codes for Enhancing the Integrity of Information Storage in NAND Flash MemoriesG. Achala0https://orcid.org/0009-0001-4613-1773U. Shripathi Acharya1Pathipati Srihari2https://orcid.org/0000-0001-9168-2753National Institute of Technology, Karnataka (NIT-K), Surathkal, IndiaNational Institute of Technology, Karnataka (NIT-K), Surathkal, IndiaNational Institute of Technology, Karnataka (NIT-K), Surathkal, IndiaThe revolution in the field of information processing systems has created a huge demand for reliable and enhanced data storage capabilities. This demand is being met by advances in channel coding algorithms along with upward scaling of the capacities of hardware devices. NAND Flash memory is a type of non-volatile memory. Scaling of the size of flash memories from Single Level Cell (SLC) devices to Multilevel cell (MLC) devices has increased the storage capacity. However, these multi-bit per cell architectures are characterized by significantly higher Raw Bit Error Rate (RBER) values when compared with SLC architectures. The requirement of low Undetected Bit Error Rate (UBER) values has motivated us to synthesize powerful channel codes for enhancing the integrity of information Storage in multi-level NAND Flash Memory devices. This paper describes the synthesis of novel Subfield Subcodes of Reed Solomon Codes (SSRS) and Reed-Solomon (RS) codes which are matched to multi-bit per cell architectures. UBER values have been calculated for each of the synthesized codes described in this paper. This allows the determination of the performance and the improvement in data storage integrity brought by using these codes. We have shown that the synthesized SSRS and RS codes can provide very low UBER even when the corresponding RBER values are appreciable. As RS codes permit the detection and correction of a greater number of errors for a given code length, their performance is superior to that of SSRS codes. This improved performance is obtained at the cost of greater complexity of encoding and decoding processes.https://ieeexplore.ieee.org/document/10179920/Bit error ratechannel codingerror correction codeflash memoryNAND flashReed-Solomon codes |
| spellingShingle | G. Achala U. Shripathi Acharya Pathipati Srihari On the Design of SSRS and RS Codes for Enhancing the Integrity of Information Storage in NAND Flash Memories IEEE Access Bit error rate channel coding error correction code flash memory NAND flash Reed-Solomon codes |
| title | On the Design of SSRS and RS Codes for Enhancing the Integrity of Information Storage in NAND Flash Memories |
| title_full | On the Design of SSRS and RS Codes for Enhancing the Integrity of Information Storage in NAND Flash Memories |
| title_fullStr | On the Design of SSRS and RS Codes for Enhancing the Integrity of Information Storage in NAND Flash Memories |
| title_full_unstemmed | On the Design of SSRS and RS Codes for Enhancing the Integrity of Information Storage in NAND Flash Memories |
| title_short | On the Design of SSRS and RS Codes for Enhancing the Integrity of Information Storage in NAND Flash Memories |
| title_sort | on the design of ssrs and rs codes for enhancing the integrity of information storage in nand flash memories |
| topic | Bit error rate channel coding error correction code flash memory NAND flash Reed-Solomon codes |
| url | https://ieeexplore.ieee.org/document/10179920/ |
| work_keys_str_mv | AT gachala onthedesignofssrsandrscodesforenhancingtheintegrityofinformationstorageinnandflashmemories AT ushripathiacharya onthedesignofssrsandrscodesforenhancingtheintegrityofinformationstorageinnandflashmemories AT pathipatisrihari onthedesignofssrsandrscodesforenhancingtheintegrityofinformationstorageinnandflashmemories |