Modified Proficient Adjacent Error Correcting Codes

As the technology scales down, the soft errors manifested from faults appear in memories due to radiation effects. This paper suggests two decoding mechanisms using hamming bits, extended hamming bits and vertical parity bits applied on matrix codes. Among the proposed two ways of decoding, the meth...

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Main Authors: Neelima K, C. Subhas
Format: Article
Language:English
Published: Elsevier 2023-09-01
Series:e-Prime: Advances in Electrical Engineering, Electronics and Energy
Subjects:
Online Access:http://www.sciencedirect.com/science/article/pii/S2772671123001729
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author Neelima K
C. Subhas
author_facet Neelima K
C. Subhas
author_sort Neelima K
collection DOAJ
description As the technology scales down, the soft errors manifested from faults appear in memories due to radiation effects. This paper suggests two decoding mechanisms using hamming bits, extended hamming bits and vertical parity bits applied on matrix codes. Among the proposed two ways of decoding, the method-2 induces less number of errors if the number of adjacent bits exceeds N/2 for N-bit data. Both decoding mechanisms are capable of correcting a maximum of N/2 adjacent errors in N data bits. The codes are modelled in Verilog HDL and are verified in Xilinx Vivado 2021.2 Tool for Zynq 7000 series FPGA. The results prove that the minimum bit overhead of 31.25% and maximum code rate of 76.19% can be achieved if 64-bits of data are processed at a time using proposed AEDAC codes but with a trade-off in terms of area.
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spelling doaj.art-ca0234f3fbd84aa38f65e93b877cac492023-09-25T04:13:01ZengElseviere-Prime: Advances in Electrical Engineering, Electronics and Energy2772-67112023-09-015100277Modified Proficient Adjacent Error Correcting CodesNeelima K0C. Subhas1Department of ECE, JNTUA Ananthapuramu, 515002 India; Corresponding author.JNTUA College of Engineering, Kalikiri, 517234 IndiaAs the technology scales down, the soft errors manifested from faults appear in memories due to radiation effects. This paper suggests two decoding mechanisms using hamming bits, extended hamming bits and vertical parity bits applied on matrix codes. Among the proposed two ways of decoding, the method-2 induces less number of errors if the number of adjacent bits exceeds N/2 for N-bit data. Both decoding mechanisms are capable of correcting a maximum of N/2 adjacent errors in N data bits. The codes are modelled in Verilog HDL and are verified in Xilinx Vivado 2021.2 Tool for Zynq 7000 series FPGA. The results prove that the minimum bit overhead of 31.25% and maximum code rate of 76.19% can be achieved if 64-bits of data are processed at a time using proposed AEDAC codes but with a trade-off in terms of area.http://www.sciencedirect.com/science/article/pii/S2772671123001729Bit overheadCode rateCode efficiencyHamming codeMatrix codeParity bits
spellingShingle Neelima K
C. Subhas
Modified Proficient Adjacent Error Correcting Codes
e-Prime: Advances in Electrical Engineering, Electronics and Energy
Bit overhead
Code rate
Code efficiency
Hamming code
Matrix code
Parity bits
title Modified Proficient Adjacent Error Correcting Codes
title_full Modified Proficient Adjacent Error Correcting Codes
title_fullStr Modified Proficient Adjacent Error Correcting Codes
title_full_unstemmed Modified Proficient Adjacent Error Correcting Codes
title_short Modified Proficient Adjacent Error Correcting Codes
title_sort modified proficient adjacent error correcting codes
topic Bit overhead
Code rate
Code efficiency
Hamming code
Matrix code
Parity bits
url http://www.sciencedirect.com/science/article/pii/S2772671123001729
work_keys_str_mv AT neelimak modifiedproficientadjacenterrorcorrectingcodes
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