Efficient pipelined flow classification for intelligent data processing in IoT

The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things (IoT). In recent years, researchers have tried to develop hardware-based solutions for the classification of Internet pac...

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Main Authors: Seyed Navid Mousavi, Fengping Chen, Mahdi Abbasi, Mohammad R. Khosravi, Milad Rafiee
Format: Article
Language:English
Published: KeAi Communications Co., Ltd. 2022-08-01
Series:Digital Communications and Networks
Subjects:
Online Access:http://www.sciencedirect.com/science/article/pii/S2352864822000591
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author Seyed Navid Mousavi
Fengping Chen
Mahdi Abbasi
Mohammad R. Khosravi
Milad Rafiee
author_facet Seyed Navid Mousavi
Fengping Chen
Mahdi Abbasi
Mohammad R. Khosravi
Milad Rafiee
author_sort Seyed Navid Mousavi
collection DOAJ
description The packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things (IoT). In recent years, researchers have tried to develop hardware-based solutions for the classification of Internet packets. Due to higher throughput and shorter delays, these solutions are considered as a major key to improving the quality of services. Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput. The proposed architectures, however, cannot reach a compromise among power consumption, memory usage, and throughput rate. In view of this, the architecture proposed in this paper contains a pipeline-based micro-core that is used in network processors to classify packets. To this end, three architectures have been implemented using the proposed micro-core. The first architecture performs parallel classification based on header fields. The second one classifies packets in a serial manner. The last architecture is the pipeline-based classifier, which can increase performance by nine times. The proposed architectures have been implemented on an FPGA chip. The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput. The architecture has a power consumption of is 1.294w, and its throughput with a frequency of 233 ​MHz exceeds 147 Gbps.
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spelling doaj.art-ca43938881194ff585bd5f15513ed2b02022-12-22T02:16:26ZengKeAi Communications Co., Ltd.Digital Communications and Networks2352-86482022-08-0184561575Efficient pipelined flow classification for intelligent data processing in IoTSeyed Navid Mousavi0Fengping Chen1Mahdi Abbasi2Mohammad R. Khosravi3Milad Rafiee4Department of Computer Engineering, Engineering Faculty, Bu-Ali Sina University, Hamedan, IranWeifang Key Laboratory of Blockchain on Agricultural Vegetables, Weifang University of Science and Technology, Shouguang, Weifang, 262700, ChinaDepartment of Computer Engineering, Engineering Faculty, Bu-Ali Sina University, Hamedan, Iran; Corresponding author.Telecommunications Group, Department of Electrical and Electronic Engineering, Shiraz University of Technology, Shiraz, IranDepartment of Computer Engineering, Engineering Faculty, Bu-Ali Sina University, Hamedan, IranThe packet classification is a fundamental process in provisioning security and quality of service for many intelligent network-embedded systems running in the Internet of Things (IoT). In recent years, researchers have tried to develop hardware-based solutions for the classification of Internet packets. Due to higher throughput and shorter delays, these solutions are considered as a major key to improving the quality of services. Most of these efforts have attempted to implement a software algorithm on the FPGA to reduce the processing time and enhance the throughput. The proposed architectures, however, cannot reach a compromise among power consumption, memory usage, and throughput rate. In view of this, the architecture proposed in this paper contains a pipeline-based micro-core that is used in network processors to classify packets. To this end, three architectures have been implemented using the proposed micro-core. The first architecture performs parallel classification based on header fields. The second one classifies packets in a serial manner. The last architecture is the pipeline-based classifier, which can increase performance by nine times. The proposed architectures have been implemented on an FPGA chip. The results are indicative of a reduction in memory usage as well as an increase in speedup and throughput. The architecture has a power consumption of is 1.294w, and its throughput with a frequency of 233 ​MHz exceeds 147 Gbps.http://www.sciencedirect.com/science/article/pii/S2352864822000591EfficiencyIntelligent flow processingIoTPacket classificationPipeline
spellingShingle Seyed Navid Mousavi
Fengping Chen
Mahdi Abbasi
Mohammad R. Khosravi
Milad Rafiee
Efficient pipelined flow classification for intelligent data processing in IoT
Digital Communications and Networks
Efficiency
Intelligent flow processing
IoT
Packet classification
Pipeline
title Efficient pipelined flow classification for intelligent data processing in IoT
title_full Efficient pipelined flow classification for intelligent data processing in IoT
title_fullStr Efficient pipelined flow classification for intelligent data processing in IoT
title_full_unstemmed Efficient pipelined flow classification for intelligent data processing in IoT
title_short Efficient pipelined flow classification for intelligent data processing in IoT
title_sort efficient pipelined flow classification for intelligent data processing in iot
topic Efficiency
Intelligent flow processing
IoT
Packet classification
Pipeline
url http://www.sciencedirect.com/science/article/pii/S2352864822000591
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