Adiabatic circuits: converter for static CMOS signals
Ultra low power applications can take great advantages from adiabatic circuitry. In this technique a multiphase system is used which consists ideally of trapezoidal voltage signals. The input signals to be processed will often come from a function block realized in static CMOS. The static rectangula...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | deu |
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Copernicus Publications
2003-01-01
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| Series: | Advances in Radio Science |
| Online Access: | http://www.adv-radio-sci.net/1/247/2003/ars-1-247-2003.pdf |
| _version_ | 1818058387905052672 |
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| author | J. Fischer E. Amirante A. Bargagli-Stoffi D. Schmitt-Landsiedel |
| author_facet | J. Fischer E. Amirante A. Bargagli-Stoffi D. Schmitt-Landsiedel |
| author_sort | J. Fischer |
| collection | DOAJ |
| description | Ultra low power applications can take great advantages from adiabatic circuitry. In this technique a multiphase system is used which consists ideally of trapezoidal voltage signals. The input signals to be processed will often come from a function block realized in static CMOS. The static rectangular signals must be converted for the oscillating multiphase system of the adiabatic circuitry. This work shows how to convert the input signals to the proposed pulse form which is synchronized to the appropriate supply voltage.</p><p style="line-height: 20px;"> By means of adder structures designed for a 0.13<i>µm</i> technology in a 4-phase system there will be demonstrated, which additional circuits are necessary for the conversion. It must be taken into account whether the data arrive in parallel or serial form. Parallel data are all in one phase and therefore it is advantageous to use an adder structure with a proper input stage, e.g. a Carry Lookahead Adder (CLA). With a serial input stage it is possible to read and to process four signals during one cycle due to the adiabatic 4-phase system. Therefore input signals with a frequency four times higher than the adiabatic clock frequency can be used. This reduces the disadvantage of the slow clock period typical for adiabatic circuits. By means of an 8 bit Ripple Carry Adder (8 bit RCA) the serial reading will be introduced. If the word width is larger than 4 bits the word can be divided in 4 bit words which are processed in parallel. This is the most efficient way to minimize the number of input lines and pads. At the same time a high throughput is achieved. |
| first_indexed | 2024-12-10T12:59:50Z |
| format | Article |
| id | doaj.art-ca48093bbaec43daa314caaa440cee98 |
| institution | Directory Open Access Journal |
| issn | 1684-9965 1684-9973 |
| language | deu |
| last_indexed | 2024-12-10T12:59:50Z |
| publishDate | 2003-01-01 |
| publisher | Copernicus Publications |
| record_format | Article |
| series | Advances in Radio Science |
| spelling | doaj.art-ca48093bbaec43daa314caaa440cee982022-12-22T01:48:00ZdeuCopernicus PublicationsAdvances in Radio Science1684-99651684-99732003-01-011247251Adiabatic circuits: converter for static CMOS signalsJ. FischerE. AmiranteA. Bargagli-StoffiD. Schmitt-LandsiedelUltra low power applications can take great advantages from adiabatic circuitry. In this technique a multiphase system is used which consists ideally of trapezoidal voltage signals. The input signals to be processed will often come from a function block realized in static CMOS. The static rectangular signals must be converted for the oscillating multiphase system of the adiabatic circuitry. This work shows how to convert the input signals to the proposed pulse form which is synchronized to the appropriate supply voltage.</p><p style="line-height: 20px;"> By means of adder structures designed for a 0.13<i>µm</i> technology in a 4-phase system there will be demonstrated, which additional circuits are necessary for the conversion. It must be taken into account whether the data arrive in parallel or serial form. Parallel data are all in one phase and therefore it is advantageous to use an adder structure with a proper input stage, e.g. a Carry Lookahead Adder (CLA). With a serial input stage it is possible to read and to process four signals during one cycle due to the adiabatic 4-phase system. Therefore input signals with a frequency four times higher than the adiabatic clock frequency can be used. This reduces the disadvantage of the slow clock period typical for adiabatic circuits. By means of an 8 bit Ripple Carry Adder (8 bit RCA) the serial reading will be introduced. If the word width is larger than 4 bits the word can be divided in 4 bit words which are processed in parallel. This is the most efficient way to minimize the number of input lines and pads. At the same time a high throughput is achieved.http://www.adv-radio-sci.net/1/247/2003/ars-1-247-2003.pdf |
| spellingShingle | J. Fischer E. Amirante A. Bargagli-Stoffi D. Schmitt-Landsiedel Adiabatic circuits: converter for static CMOS signals Advances in Radio Science |
| title | Adiabatic circuits: converter for static CMOS signals |
| title_full | Adiabatic circuits: converter for static CMOS signals |
| title_fullStr | Adiabatic circuits: converter for static CMOS signals |
| title_full_unstemmed | Adiabatic circuits: converter for static CMOS signals |
| title_short | Adiabatic circuits: converter for static CMOS signals |
| title_sort | adiabatic circuits converter for static cmos signals |
| url | http://www.adv-radio-sci.net/1/247/2003/ars-1-247-2003.pdf |
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