Vectorization Programming Based on HR DSP Using SIMD
Single instruction multiple data (SIMD) vector extension has become an essential feature of high-performance processors. Architectures such as x86, ARM, MIPS, and PowerPC have specific vector extension instruction sets and SIMD micro-architectures. Using SIMD vectorization programming can significan...
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| Format: | Article |
| Language: | English |
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MDPI AG
2023-07-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/12/13/2922 |
| _version_ | 1797591858412519424 |
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| author | Chunhu Xie Huachun Wu Jian Zhou |
| author_facet | Chunhu Xie Huachun Wu Jian Zhou |
| author_sort | Chunhu Xie |
| collection | DOAJ |
| description | Single instruction multiple data (SIMD) vector extension has become an essential feature of high-performance processors. Architectures such as x86, ARM, MIPS, and PowerPC have specific vector extension instruction sets and SIMD micro-architectures. Using SIMD vectorization programming can significantly improve the performance of application algorithms while keeping the hardware overhead low. In addition, other methods can enhance algorithm performance, such as selecting the best SIMD vectorization model for algorithms, ensuring sufficient instruction streams, implementing reasonable and effective cache data prefetching, and aligning data access and storage addresses according to instruction characteristics. The goal of this paper is three-fold. First, we introduce the basic structural characteristics of a general RISC processor, Hua Rui (HR) DSP, with a custom vector instruction set based on compatibility with an MIPS64 fixed-point and floating-point instruction set, as well as a Fei Teng (FT) processor compatible with an ARMv8 instruction set. Second, we summarize the fundamental principles of SIMD vectorization programming design for the HR DSP, which provides ideas for other scholars or engineering and technical personnel to study the algorithm performance using SIMD vectorization optimization. Third, we implement representative typical algorithms based on the HR and FT platforms and obtain experimental results that show improvement in algorithm SIMD vectorization optimization according to the vector programming design principles summarized in this article can improve the single-core performance of scalar implementation without vectorization, instruction streams, and cache data prefetching by 4–22 times for mean filter, accumulation, and matrix–matrix multiplication, which is significantly better than the performance improvement of 3–13 times for the FT platform. Moreover, the performance of matrix–matrix multiplication using the best vectorization model on the HR platform is about 84% higher than that of the common SIMD vectorization model. |
| first_indexed | 2024-03-11T01:43:22Z |
| format | Article |
| id | doaj.art-ca62c6ea39a04da0a26d3f96e8c99c03 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-11T01:43:22Z |
| publishDate | 2023-07-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-ca62c6ea39a04da0a26d3f96e8c99c032023-11-18T16:25:22ZengMDPI AGElectronics2079-92922023-07-011213292210.3390/electronics12132922Vectorization Programming Based on HR DSP Using SIMDChunhu Xie0Huachun Wu1Jian Zhou2School of Mechanical and Electronic Engineering, Wuhan University of Technology, Wuhan 430070, ChinaSchool of Mechanical and Electronic Engineering, Wuhan University of Technology, Wuhan 430070, ChinaSchool of Mechanical and Electronic Engineering, Wuhan University of Technology, Wuhan 430070, ChinaSingle instruction multiple data (SIMD) vector extension has become an essential feature of high-performance processors. Architectures such as x86, ARM, MIPS, and PowerPC have specific vector extension instruction sets and SIMD micro-architectures. Using SIMD vectorization programming can significantly improve the performance of application algorithms while keeping the hardware overhead low. In addition, other methods can enhance algorithm performance, such as selecting the best SIMD vectorization model for algorithms, ensuring sufficient instruction streams, implementing reasonable and effective cache data prefetching, and aligning data access and storage addresses according to instruction characteristics. The goal of this paper is three-fold. First, we introduce the basic structural characteristics of a general RISC processor, Hua Rui (HR) DSP, with a custom vector instruction set based on compatibility with an MIPS64 fixed-point and floating-point instruction set, as well as a Fei Teng (FT) processor compatible with an ARMv8 instruction set. Second, we summarize the fundamental principles of SIMD vectorization programming design for the HR DSP, which provides ideas for other scholars or engineering and technical personnel to study the algorithm performance using SIMD vectorization optimization. Third, we implement representative typical algorithms based on the HR and FT platforms and obtain experimental results that show improvement in algorithm SIMD vectorization optimization according to the vector programming design principles summarized in this article can improve the single-core performance of scalar implementation without vectorization, instruction streams, and cache data prefetching by 4–22 times for mean filter, accumulation, and matrix–matrix multiplication, which is significantly better than the performance improvement of 3–13 times for the FT platform. Moreover, the performance of matrix–matrix multiplication using the best vectorization model on the HR platform is about 84% higher than that of the common SIMD vectorization model.https://www.mdpi.com/2079-9292/12/13/2922DSPSIMDalgorithmcacheinstruction stream |
| spellingShingle | Chunhu Xie Huachun Wu Jian Zhou Vectorization Programming Based on HR DSP Using SIMD Electronics DSP SIMD algorithm cache instruction stream |
| title | Vectorization Programming Based on HR DSP Using SIMD |
| title_full | Vectorization Programming Based on HR DSP Using SIMD |
| title_fullStr | Vectorization Programming Based on HR DSP Using SIMD |
| title_full_unstemmed | Vectorization Programming Based on HR DSP Using SIMD |
| title_short | Vectorization Programming Based on HR DSP Using SIMD |
| title_sort | vectorization programming based on hr dsp using simd |
| topic | DSP SIMD algorithm cache instruction stream |
| url | https://www.mdpi.com/2079-9292/12/13/2922 |
| work_keys_str_mv | AT chunhuxie vectorizationprogrammingbasedonhrdspusingsimd AT huachunwu vectorizationprogrammingbasedonhrdspusingsimd AT jianzhou vectorizationprogrammingbasedonhrdspusingsimd |