Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits
In this paper, an accurate linear model of the Mueller–Muller phase detector (MMPD)-based clock and data recovery circuit (MM-CDR) is proposed, which analyzes several critical points of the MM-CDR including the linearization of the MMPD and the gain of the voter. Using our technique, the jitter betw...
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| Format: | Article |
| Language: | English |
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MDPI AG
2021-08-01
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| Series: | Electronics |
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| Online Access: | https://www.mdpi.com/2079-9292/10/16/1888 |
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| author | Tao Liu Tiejun Li Fangxu Lv Bin Liang Xuqiang Zheng Heming Wang Miaomiao Wu Dechao Lu Feng Zhao |
| author_facet | Tao Liu Tiejun Li Fangxu Lv Bin Liang Xuqiang Zheng Heming Wang Miaomiao Wu Dechao Lu Feng Zhao |
| author_sort | Tao Liu |
| collection | DOAJ |
| description | In this paper, an accurate linear model of the Mueller–Muller phase detector (MMPD)-based clock and data recovery circuit (MM-CDR) is proposed, which analyzes several critical points of the MM-CDR including the linearization of the MMPD and the gain of the voter. Using our technique, the jitter between the recovery clock and the input data can be estimated with a sub-picosecond accuracy, as demonstrated in the simulation results of a 56 Gb/s quarter-rate MM-CDR implemented in 28 nm CMOS. |
| first_indexed | 2024-03-10T08:52:59Z |
| format | Article |
| id | doaj.art-cbb6cec539fb4b659d87cf59f305a267 |
| institution | Directory Open Access Journal |
| issn | 2079-9292 |
| language | English |
| last_indexed | 2024-03-10T08:52:59Z |
| publishDate | 2021-08-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Electronics |
| spelling | doaj.art-cbb6cec539fb4b659d87cf59f305a2672023-11-22T07:24:04ZengMDPI AGElectronics2079-92922021-08-011016188810.3390/electronics10161888Analysis and Modeling of Mueller–Muller Clock and Data Recovery CircuitsTao Liu0Tiejun Li1Fangxu Lv2Bin Liang3Xuqiang Zheng4Heming Wang5Miaomiao Wu6Dechao Lu7Feng Zhao8School of Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, ChinaSchool of Computer, National University of Defense Technology, Changsha 410003, ChinaSchool of Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, ChinaSchool of Computer, National University of Defense Technology, Changsha 410003, ChinaInstitute of Microelectronics of Chinese Academy of Sciences, Beijing 100029, ChinaSchool of Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, ChinaSchool of Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, ChinaSchool of Air and Missile Defense College, Air Force Engineering University, Xi’an 710051, ChinaSchool of Information Science and Technology, University of Science and Technology of China, Hefei 230027, ChinaIn this paper, an accurate linear model of the Mueller–Muller phase detector (MMPD)-based clock and data recovery circuit (MM-CDR) is proposed, which analyzes several critical points of the MM-CDR including the linearization of the MMPD and the gain of the voter. Using our technique, the jitter between the recovery clock and the input data can be estimated with a sub-picosecond accuracy, as demonstrated in the simulation results of a 56 Gb/s quarter-rate MM-CDR implemented in 28 nm CMOS.https://www.mdpi.com/2079-9292/10/16/1888clock and data recoveryMueller–Muller phase detectorjitterjitter tolerance |
| spellingShingle | Tao Liu Tiejun Li Fangxu Lv Bin Liang Xuqiang Zheng Heming Wang Miaomiao Wu Dechao Lu Feng Zhao Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits Electronics clock and data recovery Mueller–Muller phase detector jitter jitter tolerance |
| title | Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits |
| title_full | Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits |
| title_fullStr | Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits |
| title_full_unstemmed | Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits |
| title_short | Analysis and Modeling of Mueller–Muller Clock and Data Recovery Circuits |
| title_sort | analysis and modeling of mueller muller clock and data recovery circuits |
| topic | clock and data recovery Mueller–Muller phase detector jitter jitter tolerance |
| url | https://www.mdpi.com/2079-9292/10/16/1888 |
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