Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case study

The improved k-nearest neighbor (KNN) algorithm based on class contribution and feature weighting (DCT-KNN) is a highly accurate approach. However, it requires complex computational steps which consumes much time for the classification process. A field programmable gate array (FPGA) can be used to s...

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Main Authors: Abedalmuhdi Almomany, Walaa R. Ayyad, Amin Jarrah
Format: Article
Language:English
Published: Elsevier 2022-06-01
Series:Journal of King Saud University: Computer and Information Sciences
Subjects:
Online Access:http://www.sciencedirect.com/science/article/pii/S1319157822001239
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author Abedalmuhdi Almomany
Walaa R. Ayyad
Amin Jarrah
author_facet Abedalmuhdi Almomany
Walaa R. Ayyad
Amin Jarrah
author_sort Abedalmuhdi Almomany
collection DOAJ
description The improved k-nearest neighbor (KNN) algorithm based on class contribution and feature weighting (DCT-KNN) is a highly accurate approach. However, it requires complex computational steps which consumes much time for the classification process. A field programmable gate array (FPGA) can be used to solve this drawback. However, using traditional hardware description language (HDL) to implement FPGA-based accelerators requires a high design time. Fortunately, the open computing language (OpenCL) high level parallel programming tool allows rapid and effective design on FPGA-based hardware accelerators. In this study, OpenCL has been used to examine speeding up the DCT-KNN algorithm on the FPGA parallel computing platform through applying numerous parallelization and optimization techniques. The optimized approach of the improved KNN could be used in various engineering problems that require a high speed of classification process. Classification of the COVID-19 disease is the case study used to examine this work. The experimental results show that implementing the DCT-KNN algorithm on the FPGA platform (Intel De5a-net Arria-10 device was used) gives an extremely high performance when compared to the traditional single-core-CPU based implementation. The execution time for our optimized design on the FPGA accelerator is 44 times faster than the conventional design implemented on the regular CPU-based computational platform.
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spelling doaj.art-cc172d08d89147cb89b35bfbae7baf7c2022-12-22T00:33:50ZengElsevierJournal of King Saud University: Computer and Information Sciences1319-15782022-06-0134638153827Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case studyAbedalmuhdi Almomany0Walaa R. Ayyad1Amin Jarrah2Corresponding author.; Department of Computer Engineering, Hijjawi Faculty for Engineering Technology, Yarmouk University, Irbid 21163, JordanDepartment of Computer Engineering, Hijjawi Faculty for Engineering Technology, Yarmouk University, Irbid 21163, JordanDepartment of Computer Engineering, Hijjawi Faculty for Engineering Technology, Yarmouk University, Irbid 21163, JordanThe improved k-nearest neighbor (KNN) algorithm based on class contribution and feature weighting (DCT-KNN) is a highly accurate approach. However, it requires complex computational steps which consumes much time for the classification process. A field programmable gate array (FPGA) can be used to solve this drawback. However, using traditional hardware description language (HDL) to implement FPGA-based accelerators requires a high design time. Fortunately, the open computing language (OpenCL) high level parallel programming tool allows rapid and effective design on FPGA-based hardware accelerators. In this study, OpenCL has been used to examine speeding up the DCT-KNN algorithm on the FPGA parallel computing platform through applying numerous parallelization and optimization techniques. The optimized approach of the improved KNN could be used in various engineering problems that require a high speed of classification process. Classification of the COVID-19 disease is the case study used to examine this work. The experimental results show that implementing the DCT-KNN algorithm on the FPGA platform (Intel De5a-net Arria-10 device was used) gives an extremely high performance when compared to the traditional single-core-CPU based implementation. The execution time for our optimized design on the FPGA accelerator is 44 times faster than the conventional design implemented on the regular CPU-based computational platform.http://www.sciencedirect.com/science/article/pii/S1319157822001239FPGADCT-KNNHLSHDLOPENCL
spellingShingle Abedalmuhdi Almomany
Walaa R. Ayyad
Amin Jarrah
Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case study
Journal of King Saud University: Computer and Information Sciences
FPGA
DCT-KNN
HLS
HDL
OPENCL
title Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case study
title_full Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case study
title_fullStr Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case study
title_full_unstemmed Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case study
title_short Optimized implementation of an improved KNN classification algorithm using Intel FPGA platform: Covid-19 case study
title_sort optimized implementation of an improved knn classification algorithm using intel fpga platform covid 19 case study
topic FPGA
DCT-KNN
HLS
HDL
OPENCL
url http://www.sciencedirect.com/science/article/pii/S1319157822001239
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AT walaarayyad optimizedimplementationofanimprovedknnclassificationalgorithmusingintelfpgaplatformcovid19casestudy
AT aminjarrah optimizedimplementationofanimprovedknnclassificationalgorithmusingintelfpgaplatformcovid19casestudy