Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload

Design and Implementation of a Configurable Fully Compliant DVB-S2 LDPC Encoder for High Data-Rate Downlink Payload

This work centres on designing and implementing a Low-Density Parity-Check (LDPC) Encoder on a Xilinx Field Programmable Gate Array (FPGA). The encoder will be part of the Digital Video Broadcasting Satellite 2nd generation (DVB-S2) Transmitter Intellectual Property (IP) for a High Data-Rate Downlin...

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Bibliographic Details
Main Authors: Pietro Nannipieri, Giacomo Bartolacci, Matteo Bertolucci, Luca Fanucci
Format: Article
Language:English
Published: IEEE 2024-01-01
Series:IEEE Access
Subjects:
DVB-S2
LDPC
low-density parity check
satellite
telemetry transmitter
high throughput
Online Access:https://ieeexplore.ieee.org/document/10471525/

Internet

https://ieeexplore.ieee.org/document/10471525/

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