Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors
While single-ISA heterogeneous multi-core processors are widely used in mobile computing, typical code generations optimize the code for a single target core, leaving it less suitable for the other cores in the processor. We present a microarchitecture-aware code generation methodology to mitigate t...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2019-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8688418/ |
| _version_ | 1819179489196769280 |
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| author | Junmo Park Yongin Kwon Yongjun Park Dongsuk Jeon |
| author_facet | Junmo Park Yongin Kwon Yongjun Park Dongsuk Jeon |
| author_sort | Junmo Park |
| collection | DOAJ |
| description | While single-ISA heterogeneous multi-core processors are widely used in mobile computing, typical code generations optimize the code for a single target core, leaving it less suitable for the other cores in the processor. We present a microarchitecture-aware code generation methodology to mitigate this issue. We first suggest adopting Function-Multi-Versioning (FMV) to execute application codes utilizing a core at full capacity regardless of its microarchitecture. We also propose to add a simple but powerful backend optimization pass in the compiler to further boost the performance of applicable cores. Based on these schemes, we developed an automated flow that analyzes the program and generates multiple versions of hot functions tailored to different microarchitectures. At runtime, the running core chooses an optimal version to maximize computation performance. The measurements confirm that the methodology improves the performance of Cortex-A55 and Cortex-A75 cores in Samsung's next-generation Exynos 9820 processor by 11.2% and 17.9%, respectively, while running TensorFlow Lite. |
| first_indexed | 2024-12-22T21:59:15Z |
| format | Article |
| id | doaj.art-cd1ca9451af54262b3f45f9f8ead9a90 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-22T21:59:15Z |
| publishDate | 2019-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-cd1ca9451af54262b3f45f9f8ead9a902022-12-21T18:11:11ZengIEEEIEEE Access2169-35362019-01-017523715237810.1109/ACCESS.2019.29105598688418Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile ProcessorsJunmo Park0Yongin Kwon1Yongjun Park2Dongsuk Jeon3https://orcid.org/0000-0002-0395-8076Graduate School of Convergence Science and Technology, Seoul National University, Seoul, South KoreaSystem LSI, Samsung Electronics Co., Ltd., Hwaseong, South KoreaDepartment of Computer Science, Hanyang University, Seoul, South KoreaGraduate School of Convergence Science and Technology, Seoul National University, Seoul, South KoreaWhile single-ISA heterogeneous multi-core processors are widely used in mobile computing, typical code generations optimize the code for a single target core, leaving it less suitable for the other cores in the processor. We present a microarchitecture-aware code generation methodology to mitigate this issue. We first suggest adopting Function-Multi-Versioning (FMV) to execute application codes utilizing a core at full capacity regardless of its microarchitecture. We also propose to add a simple but powerful backend optimization pass in the compiler to further boost the performance of applicable cores. Based on these schemes, we developed an automated flow that analyzes the program and generates multiple versions of hot functions tailored to different microarchitectures. At runtime, the running core chooses an optimal version to maximize computation performance. The measurements confirm that the methodology improves the performance of Cortex-A55 and Cortex-A75 cores in Samsung's next-generation Exynos 9820 processor by 11.2% and 17.9%, respectively, while running TensorFlow Lite.https://ieeexplore.ieee.org/document/8688418/Edge computingfunction multi-versioningsingle-ISA heterogeneous multi-core |
| spellingShingle | Junmo Park Yongin Kwon Yongjun Park Dongsuk Jeon Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors IEEE Access Edge computing function multi-versioning single-ISA heterogeneous multi-core |
| title | Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors |
| title_full | Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors |
| title_fullStr | Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors |
| title_full_unstemmed | Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors |
| title_short | Microarchitecture-Aware Code Generation for Deep Learning on Single-ISA Heterogeneous Multi-Core Mobile Processors |
| title_sort | microarchitecture aware code generation for deep learning on single isa heterogeneous multi core mobile processors |
| topic | Edge computing function multi-versioning single-ISA heterogeneous multi-core |
| url | https://ieeexplore.ieee.org/document/8688418/ |
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