A Two-Stage X-Band 20.7-dBm Power Amplifier in 40-nm CMOS Technology

For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In...

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Bibliographic Details
Main Authors: Zhichao Li, Shiheng Yang, Samuel B. S. Lee, Kiat Seng Yeo
Format: Article
Language:English
Published: MDPI AG 2020-12-01
Series:Electronics
Subjects:
Online Access:https://www.mdpi.com/2079-9292/9/12/2198
Description
Summary:For higher integration density, X-band power amplifiers (PAs) with CMOS technology have been widely discussed in recent publications. However, with reduced power supply voltage and device size, it is a great challenge to design a compact PA with high output power and power-added efficiency (PAE). In the proposed design, a 40-nm standard CMOS process is used for higher integration with other RF building blocks, compared with other CMOS PA designs with larger process node. Transistor cells are designed with neutralization capacitors to increase stability and gain performance of the PA. As a trade-off among gain, output power, and PAE, the transistor cells in driving stage and power stage are biased for class A and class AB operation, respectively. Both transistor cells consist of two transistors working in differential mode. Furthermore, transformer-based matching networks (TMNs) are used to realize a two-stage X-band CMOS PA with compact size. The PA achieves an effective conductivity (EC) of 117.5, which is among the highest in recently reported X-band PAs in CMOS technology. The PA also attains a saturated output power (<inline-formula><math display="inline"><semantics><msub><mi>P</mi><mrow><mi>s</mi><mi>a</mi><mi>t</mi></mrow></msub></semantics></math></inline-formula>) of 20.7 dBm, a peak PAE of <inline-formula><math display="inline"><semantics><mrow><mn>22.4</mn><mo>%</mo></mrow></semantics></math></inline-formula>, and a gain of 25.6 dB at the center frequency of 10 GHz under a 1 V supply in 40-nm CMOS.
ISSN:2079-9292