Dead Zone Minimization Using Variable-Delay Element in CP-PLL for 5G Applications

The deadzone occurring in a phase-frequency detector (PFD) is a critical parameter that affects the performance of a phase-locked loop (PLL). Though a fixed-delay element reduces the deadzone, it creates an imbalance in the pulse-arrival time and among the up and down signals to the charge pump, whi...

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Main Authors: Dharani Buddha, Umakanta Nanda
Format: Article
Language:English
Published: MDPI AG 2022-12-01
Series:Micromachines
Subjects:
Online Access:https://www.mdpi.com/2072-666X/14/1/81
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author Dharani Buddha
Umakanta Nanda
author_facet Dharani Buddha
Umakanta Nanda
author_sort Dharani Buddha
collection DOAJ
description The deadzone occurring in a phase-frequency detector (PFD) is a critical parameter that affects the performance of a phase-locked loop (PLL). Though a fixed-delay element reduces the deadzone, it creates an imbalance in the pulse-arrival time and among the up and down signals to the charge pump, which increases the phase noise in the output spectrum of the PLL. Therefore, in this work a new variable-delay element (VDE) is incorporated in the PFD to reduce the dead zone and consequently the phase noise of the PLL. The performance of the proposed PFD incorporated in PLL is analyzed using cadence virtuoso 90 nm CMOS technology, achieving a phase noise of −148.89 dBc/Hz at a frequency offset of 1 MHz, a lock time of 6.01 us, a power of 0.056 mW, and a dead zone of 110.5 ps, while operating at 3.5 GHz of frequency, making it suitable for 5G applications.
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spelling doaj.art-ced1ac98ec2b4c23840fcb0706e688672023-11-30T23:32:57ZengMDPI AGMicromachines2072-666X2022-12-011418110.3390/mi14010081Dead Zone Minimization Using Variable-Delay Element in CP-PLL for 5G ApplicationsDharani Buddha0Umakanta Nanda1School of Electronics Engineering, VIT-AP University, Amaravati 522237, Andhra Pradesh, IndiaSchool of Electronics Engineering, VIT-AP University, Amaravati 522237, Andhra Pradesh, IndiaThe deadzone occurring in a phase-frequency detector (PFD) is a critical parameter that affects the performance of a phase-locked loop (PLL). Though a fixed-delay element reduces the deadzone, it creates an imbalance in the pulse-arrival time and among the up and down signals to the charge pump, which increases the phase noise in the output spectrum of the PLL. Therefore, in this work a new variable-delay element (VDE) is incorporated in the PFD to reduce the dead zone and consequently the phase noise of the PLL. The performance of the proposed PFD incorporated in PLL is analyzed using cadence virtuoso 90 nm CMOS technology, achieving a phase noise of −148.89 dBc/Hz at a frequency offset of 1 MHz, a lock time of 6.01 us, a power of 0.056 mW, and a dead zone of 110.5 ps, while operating at 3.5 GHz of frequency, making it suitable for 5G applications.https://www.mdpi.com/2072-666X/14/1/81phase-frequency detectorphase noisevariable-delay elementlock timelock range
spellingShingle Dharani Buddha
Umakanta Nanda
Dead Zone Minimization Using Variable-Delay Element in CP-PLL for 5G Applications
Micromachines
phase-frequency detector
phase noise
variable-delay element
lock time
lock range
title Dead Zone Minimization Using Variable-Delay Element in CP-PLL for 5G Applications
title_full Dead Zone Minimization Using Variable-Delay Element in CP-PLL for 5G Applications
title_fullStr Dead Zone Minimization Using Variable-Delay Element in CP-PLL for 5G Applications
title_full_unstemmed Dead Zone Minimization Using Variable-Delay Element in CP-PLL for 5G Applications
title_short Dead Zone Minimization Using Variable-Delay Element in CP-PLL for 5G Applications
title_sort dead zone minimization using variable delay element in cp pll for 5g applications
topic phase-frequency detector
phase noise
variable-delay element
lock time
lock range
url https://www.mdpi.com/2072-666X/14/1/81
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