A Design of Fixed-Complexity Sphere Decoder Combined With Interference Mitigation Algorithm for Downlink MU-MIMO Systems
In this paper, a design and implementation of fixed-complexity sphere decoder (FSD) combined with interference mitigation algorithm for downlink (DL) multiuser (MU) multiple-input multiple-output (MIMO) system is presented. To overcome performance degradation from inter-user interference in DL MU-MI...
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| Format: | Article |
| Language: | English |
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IEEE
2022-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9913460/ |
| _version_ | 1798031161782435840 |
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| author | Minjoon Kim |
| author_facet | Minjoon Kim |
| author_sort | Minjoon Kim |
| collection | DOAJ |
| description | In this paper, a design and implementation of fixed-complexity sphere decoder (FSD) combined with interference mitigation algorithm for downlink (DL) multiuser (MU) multiple-input multiple-output (MIMO) system is presented. To overcome performance degradation from inter-user interference in DL MU-MIMO systems, a hardware friendly optimized interference mitigation algorithm is proposed. The proposed algorithm achieves 0.5 dB near-optimal performance, which is 4 dB better than existing interference whitening filter for the soft-output decision. In this paper, both hard and soft-output FSD detectors are implemented with the proposed interference mitigation algorithm to function <inline-formula> <tex-math notation="LaTeX">$4\times 4$ </tex-math></inline-formula> antenna MIMO detection and interference mitigation for 4 additional streams. A fully pipelined architecture is employed to support 3.6 Gbps at 150 MHz for signals modulated by 64-QAM. From the synthesis result, the designed symbol detector has a gate count of 887 K for the FSD without pre-processor and a gate count of 1220 K for interference mitigation. By comparing previously implemented MIMO detectors, the proposed design represents a promising architecture for DL MU-MIMO systems in terms of significant performance improvement relative to inter-user interference and the compatible hardware implementation maintaining high-throughput within acceptable gate count. |
| first_indexed | 2024-04-11T19:53:03Z |
| format | Article |
| id | doaj.art-cf7743e0c5e74d8e9779eac607d48385 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-11T19:53:03Z |
| publishDate | 2022-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-cf7743e0c5e74d8e9779eac607d483852022-12-22T04:06:15ZengIEEEIEEE Access2169-35362022-01-011010788810790010.1109/ACCESS.2022.32127659913460A Design of Fixed-Complexity Sphere Decoder Combined With Interference Mitigation Algorithm for Downlink MU-MIMO SystemsMinjoon Kim0https://orcid.org/0000-0001-9361-1991Korea Electronics Technology Institute, Seongnam-si, South KoreaIn this paper, a design and implementation of fixed-complexity sphere decoder (FSD) combined with interference mitigation algorithm for downlink (DL) multiuser (MU) multiple-input multiple-output (MIMO) system is presented. To overcome performance degradation from inter-user interference in DL MU-MIMO systems, a hardware friendly optimized interference mitigation algorithm is proposed. The proposed algorithm achieves 0.5 dB near-optimal performance, which is 4 dB better than existing interference whitening filter for the soft-output decision. In this paper, both hard and soft-output FSD detectors are implemented with the proposed interference mitigation algorithm to function <inline-formula> <tex-math notation="LaTeX">$4\times 4$ </tex-math></inline-formula> antenna MIMO detection and interference mitigation for 4 additional streams. A fully pipelined architecture is employed to support 3.6 Gbps at 150 MHz for signals modulated by 64-QAM. From the synthesis result, the designed symbol detector has a gate count of 887 K for the FSD without pre-processor and a gate count of 1220 K for interference mitigation. By comparing previously implemented MIMO detectors, the proposed design represents a promising architecture for DL MU-MIMO systems in terms of significant performance improvement relative to inter-user interference and the compatible hardware implementation maintaining high-throughput within acceptable gate count.https://ieeexplore.ieee.org/document/9913460/Fixed-complexity sphere decoder (FSD)inter-user interferenceMIMO detectionmultiuser multi-input multi-output (MU-MIMO)VLSI design |
| spellingShingle | Minjoon Kim A Design of Fixed-Complexity Sphere Decoder Combined With Interference Mitigation Algorithm for Downlink MU-MIMO Systems IEEE Access Fixed-complexity sphere decoder (FSD) inter-user interference MIMO detection multiuser multi-input multi-output (MU-MIMO) VLSI design |
| title | A Design of Fixed-Complexity Sphere Decoder Combined With Interference Mitigation Algorithm for Downlink MU-MIMO Systems |
| title_full | A Design of Fixed-Complexity Sphere Decoder Combined With Interference Mitigation Algorithm for Downlink MU-MIMO Systems |
| title_fullStr | A Design of Fixed-Complexity Sphere Decoder Combined With Interference Mitigation Algorithm for Downlink MU-MIMO Systems |
| title_full_unstemmed | A Design of Fixed-Complexity Sphere Decoder Combined With Interference Mitigation Algorithm for Downlink MU-MIMO Systems |
| title_short | A Design of Fixed-Complexity Sphere Decoder Combined With Interference Mitigation Algorithm for Downlink MU-MIMO Systems |
| title_sort | design of fixed complexity sphere decoder combined with interference mitigation algorithm for downlink mu mimo systems |
| topic | Fixed-complexity sphere decoder (FSD) inter-user interference MIMO detection multiuser multi-input multi-output (MU-MIMO) VLSI design |
| url | https://ieeexplore.ieee.org/document/9913460/ |
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