New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation
We present here a simple three P-type MOSFET-based grounded memristor emulator model. The model is designed to achieve zero static power dissipation and is done so by eliminating the external DC supply i.e., no DC bias. The proposed memristor emulator model has extremely low dynamic power dissipatio...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2023-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/10015735/ |
| _version_ | 1797902250407886848 |
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| author | Prashant Kumar Pushkar Srivastava Rajeev Kumar Ranjan Montree Kumngern |
| author_facet | Prashant Kumar Pushkar Srivastava Rajeev Kumar Ranjan Montree Kumngern |
| author_sort | Prashant Kumar |
| collection | DOAJ |
| description | We present here a simple three P-type MOSFET-based grounded memristor emulator model. The model is designed to achieve zero static power dissipation and is done so by eliminating the external DC supply i.e., no DC bias. The proposed memristor emulator model has extremely low dynamic power dissipation as well which comes to around 175 nW i.e., <inline-formula> <tex-math notation="LaTeX">$\sim ~67\%$ </tex-math></inline-formula> improvement compared to recent work. A mathematical analysis is carried out to present the relevance of this design. Simulations were done on Cadence Virtuoso 90 nm technology node and fingerprints of the proposed memristor emulator were obtained. The layout area occupied by the model is approx <inline-formula> <tex-math notation="LaTeX">$1154.69~\mu \text{m}^{2}$ </tex-math></inline-formula> and an external capacitor is connected to add tunability to the circuit. Furthermore, Monte Carlo and corner analysis validate the robust nature of the design. Besides, simulations have been experimentally verified using CD-4007 CMOS integrated circuit (IC) to make the design practically feasible. Furthermore, the design offers advantages such as extremely less overall power consumption and smaller chip area that could possibly pave the path for fabrication using standard CMOS technologies. At last, an application of the proposed model depicting in-memory computation through a memristor emulator crossbar array is presented in brief. |
| first_indexed | 2024-04-10T09:14:43Z |
| format | Article |
| id | doaj.art-cf82139f5dca4fe1b3655dbf3d7e3242 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-04-10T09:14:43Z |
| publishDate | 2023-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-cf82139f5dca4fe1b3655dbf3d7e32422023-02-21T00:02:13ZengIEEEIEEE Access2169-35362023-01-01115609561610.1109/ACCESS.2023.323642410015735New Zero Power Memristor Emulator Model and Its Application in Memristive Neural ComputationPrashant Kumar0https://orcid.org/0000-0002-4404-9696Pushkar Srivastava1Rajeev Kumar Ranjan2https://orcid.org/0000-0001-7175-2611Montree Kumngern3https://orcid.org/0000-0002-1960-9081Department of Electronics Engineering, Indian Institute of Technology (ISM), Dhanbad, Jharkhand, IndiaDepartment of Electronics Engineering, Indian Institute of Technology (ISM), Dhanbad, Jharkhand, IndiaDepartment of Electronics Engineering, Indian Institute of Technology (ISM), Dhanbad, Jharkhand, IndiaDepartment of Telecommunications Engineering, School of Engineering, King Mongkut’s Institute of Technology Ladkrabang, Bangkok, ThailandWe present here a simple three P-type MOSFET-based grounded memristor emulator model. The model is designed to achieve zero static power dissipation and is done so by eliminating the external DC supply i.e., no DC bias. The proposed memristor emulator model has extremely low dynamic power dissipation as well which comes to around 175 nW i.e., <inline-formula> <tex-math notation="LaTeX">$\sim ~67\%$ </tex-math></inline-formula> improvement compared to recent work. A mathematical analysis is carried out to present the relevance of this design. Simulations were done on Cadence Virtuoso 90 nm technology node and fingerprints of the proposed memristor emulator were obtained. The layout area occupied by the model is approx <inline-formula> <tex-math notation="LaTeX">$1154.69~\mu \text{m}^{2}$ </tex-math></inline-formula> and an external capacitor is connected to add tunability to the circuit. Furthermore, Monte Carlo and corner analysis validate the robust nature of the design. Besides, simulations have been experimentally verified using CD-4007 CMOS integrated circuit (IC) to make the design practically feasible. Furthermore, the design offers advantages such as extremely less overall power consumption and smaller chip area that could possibly pave the path for fabrication using standard CMOS technologies. At last, an application of the proposed model depicting in-memory computation through a memristor emulator crossbar array is presented in brief.https://ieeexplore.ieee.org/document/10015735/Memristor emulatorCMOSpinched hysteresis loop (PHL)Monte Carloin-memory computation |
| spellingShingle | Prashant Kumar Pushkar Srivastava Rajeev Kumar Ranjan Montree Kumngern New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation IEEE Access Memristor emulator CMOS pinched hysteresis loop (PHL) Monte Carlo in-memory computation |
| title | New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation |
| title_full | New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation |
| title_fullStr | New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation |
| title_full_unstemmed | New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation |
| title_short | New Zero Power Memristor Emulator Model and Its Application in Memristive Neural Computation |
| title_sort | new zero power memristor emulator model and its application in memristive neural computation |
| topic | Memristor emulator CMOS pinched hysteresis loop (PHL) Monte Carlo in-memory computation |
| url | https://ieeexplore.ieee.org/document/10015735/ |
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