A Novel Scheme for Fault-Tolerant And Higher Capacity Network on Chip
As CMOS technology scales down, NoC (Network on Chip) gradually becomes the mainstream of onchip communication. In this paper we present a methodology to design fault-tolerant routing algorithms for regular direct interconnection networks. It supports fully adaptive routing, does not degrade perfor...
Main Authors: | Maryam Raiyat Aliabadi, Ahmad Khadem zadeh, Mohammad Raiyat Aliabadi |
---|---|
Format: | Article |
Language: | English |
Published: |
Iran Telecom Research Center
2010-03-01
|
Series: | International Journal of Information and Communication Technology Research |
Subjects: | |
Online Access: | http://ijict.itrc.ac.ir/article-1-270-en.html |
Similar Items
-
An Adaptive Routing Algorithm for Wireless Network on Chips
by: A. Tajary, et al.
Published: (2022-07-01) -
Virtual Coordinate System Based on a Circulant Topology for Routing in Networks-On-Chip
by: Andrei M. Sukhov, et al.
Published: (2024-01-01) -
Enhanced overloaded code division multiple access for network on chip
by: Behnam Vakili, et al.
Published: (2022-03-01) -
ARTEMIS: A Simulator Tool for Heterogeneous Network-on-Chip
by: Fatemeh Vardi, et al.
Published: (2017-06-01) -
A Network Adaptive Fault-Tolerant Routing Algorithm for Demanding Latency and Throughput Applications of Network-on-a-Chip Designs
by: Zulqar Nain, et al.
Published: (2020-07-01)