Comprehensive Design of Device Parameters for GaN Vertical Trench MOSFETs

In this work, device parameters for GaN vertical trench MOSFETs have been investigated systematically to further improve the device characteristics. The n<sup>-</sup> GaN drift layer, the p<sup>+</sup> GaN layer and the trench gate are designed and optimized systematically us...

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Bibliographic Details
Main Authors: Shuang Liu, Xiufeng Song, Jincheng Zhang, Shenglei Zhao, Jun Luo, Hong Zhang, Yachao Zhang, Weihang Zhang, Hong Zhou, Zhihong Liu, Yue Hao
Format: Article
Language:English
Published: IEEE 2020-01-01
Series:IEEE Access
Subjects:
Online Access:https://ieeexplore.ieee.org/document/9019679/
Description
Summary:In this work, device parameters for GaN vertical trench MOSFETs have been investigated systematically to further improve the device characteristics. The n<sup>-</sup> GaN drift layer, the p<sup>+</sup> GaN layer and the trench gate are designed and optimized systematically using Silvaco ATLAS 2-D simulation, in order to get the best trade-off between VBR and specific on-resistance R<sub>on</sub>. Three-terminal breakdown curves, the electron concentration, current density and electric field strength distributions have been presented to analyze the breakdown characteristics. The correlations between different parameters and different initial conditions are considered, and the eight parameters are optimized comprehensively. After the final optimization, record high FOM of 4.8 GW/cm<sup>2</sup>, V<sub>BR</sub> of 2783 V, average electric field E<sub>drift</sub> of 1.98 MV/cm and a low R<sub>on</sub> of 1.6 m&#x03A9;&#x00B7;cm<sup>2</sup> are obtained for drift layer thickness of 14 &#x03BC;m. The product of the thickness L<sub>p</sub> and doping density N<sub>p</sub> of p<sup>+</sup> GaN layer can determine the breakdown mechanism, and punch through mechanism would occur when Lp &#x00B7;N<sub>p</sub> is lower than a certain value. The results indicate there exists large optimization room for fabricated GaN vertical trench MOSFETs, and the device characteristics can be further improved through the methodology in this paper for high power and high voltage applications.
ISSN:2169-3536