Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking
This paper presents an improved reversible contrast mapping (RCM) algorithm for reversible invisible watermarking (RIW) in both software and hardware platforms. Based on well-known parameters for RIW like distortion, embedding bit rate, payload size and data hiding capacity, an efficient embedding b...
| Main Authors: | , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2020-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9060891/ |
| _version_ | 1831589180551987200 |
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| author | Subhajit Das Arun Kumar Sunaniya Reshmi Maity Niladri Pratap Maity |
| author_facet | Subhajit Das Arun Kumar Sunaniya Reshmi Maity Niladri Pratap Maity |
| author_sort | Subhajit Das |
| collection | DOAJ |
| description | This paper presents an improved reversible contrast mapping (RCM) algorithm for reversible invisible watermarking (RIW) in both software and hardware platforms. Based on well-known parameters for RIW like distortion, embedding bit rate, payload size and data hiding capacity, an efficient embedding bit rate control based contrast mapping (EBCRCM) algorithm is proposed. An adaptive linear contrast mapping on pixel intensity value is asserted with RCM that controls the embedding bit rate without changing the embedding capacity to maintain distortion. Xilinx system generator (XSG) and VIVADO tool construct the novel VLSI architecture that needs 173.362 ns latency for 100 MHz clock with throughput 46.146 Mbps and 5.8 ns critical path for single cycle of embedding process. The proposed algorithm is verified in MATLAB tool based software platform by taking different types of multimedia data like gray-scale images, color images and video signals. Implementation of low hardware resources based VLSI architecture through zed-board in real time field programmable gate array (FPGA) platform confirms the capability of high speed, low cost and real-time use. 100% agreement is observed from software simulations and hardware platforms. |
| first_indexed | 2024-12-18T00:39:40Z |
| format | Article |
| id | doaj.art-d14b2843b4204f52b7feee5cf7756306 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-18T00:39:40Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-d14b2843b4204f52b7feee5cf77563062022-12-21T21:26:56ZengIEEEIEEE Access2169-35362020-01-018690726909510.1109/ACCESS.2020.29861349060891Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible WatermarkingSubhajit Das0https://orcid.org/0000-0001-9500-6656Arun Kumar Sunaniya1Reshmi Maity2Niladri Pratap Maity3Department of Electronics and Instrumentation Engineering, National Institute of Technology, Silchar, IndiaDepartment of Electronics and Instrumentation Engineering, National Institute of Technology, Silchar, IndiaDepartment of Electronics and Communication Engineering, Mizoram University, (A Central University, Government of India), Tanhril, IndiaDepartment of Electronics and Communication Engineering, Mizoram University, (A Central University, Government of India), Tanhril, IndiaThis paper presents an improved reversible contrast mapping (RCM) algorithm for reversible invisible watermarking (RIW) in both software and hardware platforms. Based on well-known parameters for RIW like distortion, embedding bit rate, payload size and data hiding capacity, an efficient embedding bit rate control based contrast mapping (EBCRCM) algorithm is proposed. An adaptive linear contrast mapping on pixel intensity value is asserted with RCM that controls the embedding bit rate without changing the embedding capacity to maintain distortion. Xilinx system generator (XSG) and VIVADO tool construct the novel VLSI architecture that needs 173.362 ns latency for 100 MHz clock with throughput 46.146 Mbps and 5.8 ns critical path for single cycle of embedding process. The proposed algorithm is verified in MATLAB tool based software platform by taking different types of multimedia data like gray-scale images, color images and video signals. Implementation of low hardware resources based VLSI architecture through zed-board in real time field programmable gate array (FPGA) platform confirms the capability of high speed, low cost and real-time use. 100% agreement is observed from software simulations and hardware platforms.https://ieeexplore.ieee.org/document/9060891/Reversible image watermarkingreversible contrast mappingXilinx system generatorFPGA |
| spellingShingle | Subhajit Das Arun Kumar Sunaniya Reshmi Maity Niladri Pratap Maity Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking IEEE Access Reversible image watermarking reversible contrast mapping Xilinx system generator FPGA |
| title | Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking |
| title_full | Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking |
| title_fullStr | Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking |
| title_full_unstemmed | Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking |
| title_short | Parallel Hardware Implementation of Efficient Embedding Bit Rate Control Based Contrast Mapping Algorithm for Reversible Invisible Watermarking |
| title_sort | parallel hardware implementation of efficient embedding bit rate control based contrast mapping algorithm for reversible invisible watermarking |
| topic | Reversible image watermarking reversible contrast mapping Xilinx system generator FPGA |
| url | https://ieeexplore.ieee.org/document/9060891/ |
| work_keys_str_mv | AT subhajitdas parallelhardwareimplementationofefficientembeddingbitratecontrolbasedcontrastmappingalgorithmforreversibleinvisiblewatermarking AT arunkumarsunaniya parallelhardwareimplementationofefficientembeddingbitratecontrolbasedcontrastmappingalgorithmforreversibleinvisiblewatermarking AT reshmimaity parallelhardwareimplementationofefficientembeddingbitratecontrolbasedcontrastmappingalgorithmforreversibleinvisiblewatermarking AT niladripratapmaity parallelhardwareimplementationofefficientembeddingbitratecontrolbasedcontrastmappingalgorithmforreversibleinvisiblewatermarking |