Asynchronous Register Less NULL Convention Logic (RL-NCL) Pipeline Architectures Using Basic Gates
Asynchronous circuits is an alternative to design digital systems that is becoming the interest of many researchers in the digital design area mainly due to it’s low-power consumption and robustness. One of the most compelling design paradigms of asynchronous circuits is the NULL Convention Logic (...
| Main Authors: | , |
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| Format: | Article |
| Language: | English |
| Published: |
Universidad de Montevideo
2022-12-01
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| Series: | Memoria Investigaciones en Ingeniería |
| Subjects: | |
| Online Access: | http://revistas.um.edu.uy/index.php/ingenieria/article/view/1111 |
| _version_ | 1797979130767081472 |
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| author | Gabriel C. Duarte Duarte L. Oliveira |
| author_facet | Gabriel C. Duarte Duarte L. Oliveira |
| author_sort | Gabriel C. Duarte |
| collection | DOAJ |
| description |
Asynchronous circuits is an alternative to design digital systems that is becoming the interest of many researchers in the digital design area mainly due to it’s low-power consumption and robustness. One of the most compelling design paradigms of asynchronous circuits is the NULL Convention Logic (NCL). The pipeline is a very common technique used in digital circuits to achieve high throughput. Although one can implement a pipeline using NCL gates, recent works have shown that register-less pipelines are possible using modified NCL gates. In this paper we propose two new Register-Less NCL (RL-NCL) pipeline architectures and two new methods to design NCL gates, which can be implemented even in Field Programmable Gate Arrays (FPGAs) or using the standard cells method. The new design of the proposed architecture was able to achieve an average area reduction of 27,32%, an average latency reduction of 14,1% and an average throughput increase of 5,54% comparing with the conventional NCL pipeline architecture.
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| first_indexed | 2024-04-11T05:35:09Z |
| format | Article |
| id | doaj.art-d3ea9962e6704dcebd9907d5b757576b |
| institution | Directory Open Access Journal |
| issn | 2301-1092 2301-1106 |
| language | English |
| last_indexed | 2024-04-11T05:35:09Z |
| publishDate | 2022-12-01 |
| publisher | Universidad de Montevideo |
| record_format | Article |
| series | Memoria Investigaciones en Ingeniería |
| spelling | doaj.art-d3ea9962e6704dcebd9907d5b757576b2022-12-22T14:57:26ZengUniversidad de MontevideoMemoria Investigaciones en Ingeniería2301-10922301-11062022-12-012310.36561/ING.23.7Asynchronous Register Less NULL Convention Logic (RL-NCL) Pipeline Architectures Using Basic GatesGabriel C. Duarte0Duarte L. Oliveira1Aeronautical Technological Institute, BrasilAeronautical Technological Institute, Brasil Asynchronous circuits is an alternative to design digital systems that is becoming the interest of many researchers in the digital design area mainly due to it’s low-power consumption and robustness. One of the most compelling design paradigms of asynchronous circuits is the NULL Convention Logic (NCL). The pipeline is a very common technique used in digital circuits to achieve high throughput. Although one can implement a pipeline using NCL gates, recent works have shown that register-less pipelines are possible using modified NCL gates. In this paper we propose two new Register-Less NCL (RL-NCL) pipeline architectures and two new methods to design NCL gates, which can be implemented even in Field Programmable Gate Arrays (FPGAs) or using the standard cells method. The new design of the proposed architecture was able to achieve an average area reduction of 27,32%, an average latency reduction of 14,1% and an average throughput increase of 5,54% comparing with the conventional NCL pipeline architecture. http://revistas.um.edu.uy/index.php/ingenieria/article/view/1111Asynchronous CircuitsNCLRL-NCLFPGAPipeline |
| spellingShingle | Gabriel C. Duarte Duarte L. Oliveira Asynchronous Register Less NULL Convention Logic (RL-NCL) Pipeline Architectures Using Basic Gates Memoria Investigaciones en Ingeniería Asynchronous Circuits NCL RL-NCL FPGA Pipeline |
| title | Asynchronous Register Less NULL Convention Logic (RL-NCL) Pipeline Architectures Using Basic Gates |
| title_full | Asynchronous Register Less NULL Convention Logic (RL-NCL) Pipeline Architectures Using Basic Gates |
| title_fullStr | Asynchronous Register Less NULL Convention Logic (RL-NCL) Pipeline Architectures Using Basic Gates |
| title_full_unstemmed | Asynchronous Register Less NULL Convention Logic (RL-NCL) Pipeline Architectures Using Basic Gates |
| title_short | Asynchronous Register Less NULL Convention Logic (RL-NCL) Pipeline Architectures Using Basic Gates |
| title_sort | asynchronous register less null convention logic rl ncl pipeline architectures using basic gates |
| topic | Asynchronous Circuits NCL RL-NCL FPGA Pipeline |
| url | http://revistas.um.edu.uy/index.php/ingenieria/article/view/1111 |
| work_keys_str_mv | AT gabrielcduarte asynchronousregisterlessnullconventionlogicrlnclpipelinearchitecturesusingbasicgates AT duarteloliveira asynchronousregisterlessnullconventionlogicrlnclpipelinearchitecturesusingbasicgates |