Front-End Gateway System With Serial Communication Protocol Conversion and Edge Computing Platforms - Guo-Ming Sung; Li-Fen Tung; Chih-Jung Huang; Chih-Ping Yu (IEEE Access, 2023)
This study presents a front-end gateway system with asynchronous and synchronous serial communication protocol conversion between a universal asynchronous receiver/transmitter (UART) protocol and an inter-integrated circuit (I2C) protocol. The valid data and sensing data can be integrated using the I2C protocol and sent to an edge computing platform for automated data analysis. Our system reduces the data processing time and the number of buses. The system has an edge computing platform that handles simple linear regression, base conversion, a neural network, and a text database and communicates with multiple peripheral devices. The I2C master and slave are constructed on the edge computing platform and implement arbitration by using the carrier-sense multiple access with collision avoidance protocol to prevent data collision. According to the results obtained from the Signal Tap logic analyzer in experiments conducted using a field-programmable gate array board, a completed 330-bit UART packet requires $755.2~μ \text{s}$ to be received, and the throughput is 436.97 kbps. By contrast, a 90-bit I2C packet requires $184.6~μ \text{s}$ to be received, and the throughput is 487.54 kbps. The front-end gateway sends integrated packets by using the I2C protocol, and the operating freuency (serial clock) of the I2C slave can reach up to 3.6 MHz bidirectionally. An integrated 153-bit packet requires $42.96~μ \text{s}$ to be received by the edge computing platform, and the throughput is 3.5614 Mbps, which is approximately 8.15 times higher than that of the UART packet. We also fabricated a front-end gateway ASIC by using the TSMC 90-nm 1P9M CMOS process.