Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5
In this paper, a new 32-bit ASIP-based crypto processor for AES, IDEA, and MD5 is designed. The instruction-set consists of both general purpose and specific instructions for the above cryptographic algorithms. The proposed architecture has nine function units and two data buses. It has also two typ...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
| Published: |
Elsevier
2017-08-01
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| Series: | Engineering Science and Technology, an International Journal |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2215098617300885 |
| _version_ | 1811309392221437952 |
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| author | Karim Shahbazi Mohammad Eshghi Reza Faghih Mirzaee |
| author_facet | Karim Shahbazi Mohammad Eshghi Reza Faghih Mirzaee |
| author_sort | Karim Shahbazi |
| collection | DOAJ |
| description | In this paper, a new 32-bit ASIP-based crypto processor for AES, IDEA, and MD5 is designed. The instruction-set consists of both general purpose and specific instructions for the above cryptographic algorithms. The proposed architecture has nine function units and two data buses. It has also two types of 32-bit instruction formats for executing Memory Reference (M.R.), Register Reference (R.R.), and Input/Output Reference (I/O R.) instructions. The maximum achieved frequency is 166.916 MHz. The encoded output results of the encryption process of a 128-bit input block are obtained after 122, 146 and 170 clock cycles for AES-128, AES-192, and AES-256, respectively. Moreover, it takes 95 clock cycles to encrypt or decrypt a 64-bit input block by using IDEA. Finally, the MD5 hash algorithm requires 469 clock cycles to generate the coded outputs for a block of 512 bits. The performance of the proposed processor is compared to some previous and state-of-the-art implementations in terms of speed, latency, throughput, and flexibility. |
| first_indexed | 2024-04-13T09:41:19Z |
| format | Article |
| id | doaj.art-d6084008285c4e69bc9063c24b388933 |
| institution | Directory Open Access Journal |
| issn | 2215-0986 |
| language | English |
| last_indexed | 2024-04-13T09:41:19Z |
| publishDate | 2017-08-01 |
| publisher | Elsevier |
| record_format | Article |
| series | Engineering Science and Technology, an International Journal |
| spelling | doaj.art-d6084008285c4e69bc9063c24b3889332022-12-22T02:51:54ZengElsevierEngineering Science and Technology, an International Journal2215-09862017-08-012041308131710.1016/j.jestch.2017.07.002Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5Karim Shahbazi0Mohammad Eshghi1Reza Faghih Mirzaee2Young Researchers and Elite Club, Arak Branch, Islamic Azad University, Arak, IranFaculty of Electrical and Computer Engineering, Shahid Beheshti University, G.C., Tehran, IranDepartment of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, IranIn this paper, a new 32-bit ASIP-based crypto processor for AES, IDEA, and MD5 is designed. The instruction-set consists of both general purpose and specific instructions for the above cryptographic algorithms. The proposed architecture has nine function units and two data buses. It has also two types of 32-bit instruction formats for executing Memory Reference (M.R.), Register Reference (R.R.), and Input/Output Reference (I/O R.) instructions. The maximum achieved frequency is 166.916 MHz. The encoded output results of the encryption process of a 128-bit input block are obtained after 122, 146 and 170 clock cycles for AES-128, AES-192, and AES-256, respectively. Moreover, it takes 95 clock cycles to encrypt or decrypt a 64-bit input block by using IDEA. Finally, the MD5 hash algorithm requires 469 clock cycles to generate the coded outputs for a block of 512 bits. The performance of the proposed processor is compared to some previous and state-of-the-art implementations in terms of speed, latency, throughput, and flexibility.http://www.sciencedirect.com/science/article/pii/S2215098617300885ASIPAESCrypto ProcessorIDEAMD5 |
| spellingShingle | Karim Shahbazi Mohammad Eshghi Reza Faghih Mirzaee Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5 Engineering Science and Technology, an International Journal ASIP AES Crypto Processor IDEA MD5 |
| title | Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5 |
| title_full | Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5 |
| title_fullStr | Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5 |
| title_full_unstemmed | Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5 |
| title_short | Design and implementation of an ASIP-based cryptography processor for AES, IDEA, and MD5 |
| title_sort | design and implementation of an asip based cryptography processor for aes idea and md5 |
| topic | ASIP AES Crypto Processor IDEA MD5 |
| url | http://www.sciencedirect.com/science/article/pii/S2215098617300885 |
| work_keys_str_mv | AT karimshahbazi designandimplementationofanasipbasedcryptographyprocessorforaesideaandmd5 AT mohammadeshghi designandimplementationofanasipbasedcryptographyprocessorforaesideaandmd5 AT rezafaghihmirzaee designandimplementationofanasipbasedcryptographyprocessorforaesideaandmd5 |