Memory disambiguation hardware: a Review
One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has gene...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
Postgraduate Office, School of Computer Science, Universidad Nacional de La Plata
2008-10-01
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| Series: | Journal of Computer Science and Technology |
| Subjects: | |
| Online Access: | https://journal.info.unlp.edu.ar/JCST/article/view/754 |
| Summary: | One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has generated a large body of work on optimizing address-based memory disambiguation logic, namely the load-store queue. In this paper we review the most significant proposals in this research field, focusing on our own contributions. |
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| ISSN: | 1666-6046 1666-6038 |