Memory disambiguation hardware: a Review
One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has gene...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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Postgraduate Office, School of Computer Science, Universidad Nacional de La Plata
2008-10-01
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| Series: | Journal of Computer Science and Technology |
| Subjects: | |
| Online Access: | https://journal.info.unlp.edu.ar/JCST/article/view/754 |
| _version_ | 1818864388087480320 |
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| author | Fernando Castro Daniel Chaver Luis Piñuel Manuel Prieto Francisco Tirado Fernández |
| author_facet | Fernando Castro Daniel Chaver Luis Piñuel Manuel Prieto Francisco Tirado Fernández |
| author_sort | Fernando Castro |
| collection | DOAJ |
| description | One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has generated a large body of work on optimizing address-based memory disambiguation logic, namely the load-store queue. In this paper we review the most significant proposals in this research field, focusing on our own contributions. |
| first_indexed | 2024-12-19T10:30:51Z |
| format | Article |
| id | doaj.art-d61ecc29be0347399226fb2a4f204104 |
| institution | Directory Open Access Journal |
| issn | 1666-6046 1666-6038 |
| language | English |
| last_indexed | 2024-12-19T10:30:51Z |
| publishDate | 2008-10-01 |
| publisher | Postgraduate Office, School of Computer Science, Universidad Nacional de La Plata |
| record_format | Article |
| series | Journal of Computer Science and Technology |
| spelling | doaj.art-d61ecc29be0347399226fb2a4f2041042022-12-21T20:25:46ZengPostgraduate Office, School of Computer Science, Universidad Nacional de La PlataJournal of Computer Science and Technology1666-60461666-60382008-10-01803132138448Memory disambiguation hardware: a ReviewFernando Castro0Daniel Chaver1Luis Piñuel2Manuel Prieto3Francisco Tirado Fernández4ArTeCS Group, Department of Computer Arquitecture, Complutense University, Madrid, SpainArTeCS Group, Department of Computer Arquitecture, Complutense University, Madrid, SpainArTeCS Group, Department of Computer Arquitecture, Complutense University, Madrid, SpainArTeCS Group, Department of Computer Arquitecture, Complutense University, Madrid, SpainArTeCS Group, Department of Computer Arquitecture, Complutense University, Madrid, SpainOne of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has generated a large body of work on optimizing address-based memory disambiguation logic, namely the load-store queue. In this paper we review the most significant proposals in this research field, focusing on our own contributions.https://journal.info.unlp.edu.ar/JCST/article/view/754lsqmemory disambiguationenergy-efficiencyfilteringhardware simplification |
| spellingShingle | Fernando Castro Daniel Chaver Luis Piñuel Manuel Prieto Francisco Tirado Fernández Memory disambiguation hardware: a Review Journal of Computer Science and Technology lsq memory disambiguation energy-efficiency filtering hardware simplification |
| title | Memory disambiguation hardware: a Review |
| title_full | Memory disambiguation hardware: a Review |
| title_fullStr | Memory disambiguation hardware: a Review |
| title_full_unstemmed | Memory disambiguation hardware: a Review |
| title_short | Memory disambiguation hardware: a Review |
| title_sort | memory disambiguation hardware a review |
| topic | lsq memory disambiguation energy-efficiency filtering hardware simplification |
| url | https://journal.info.unlp.edu.ar/JCST/article/view/754 |
| work_keys_str_mv | AT fernandocastro memorydisambiguationhardwareareview AT danielchaver memorydisambiguationhardwareareview AT luispinuel memorydisambiguationhardwareareview AT manuelprieto memorydisambiguationhardwareareview AT franciscotiradofernandez memorydisambiguationhardwareareview |