Memory disambiguation hardware: a Review

Memory disambiguation hardware: a Review

One of the main challenges of modern processor designs is the implementation of scalable and efficient mechanisms to detect memory access order violations as a result of out-of-order execution. Conventional structures performing this task are complex, inefficient and power-hungry. This fact has gene...

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Bibliographic Details
Main Authors:	Fernando Castro, Daniel Chaver, Luis Piñuel, Manuel Prieto, Francisco Tirado Fernández
Format:	Article
Language:	English
Published:	Postgraduate Office, School of Computer Science, Universidad Nacional de La Plata 2008-10-01
Series:	Journal of Computer Science and Technology
Subjects:	lsq memory disambiguation energy-efficiency filtering hardware simplification
Online Access:	https://journal.info.unlp.edu.ar/JCST/article/view/754

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