A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme
This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) sch...
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MDPI AG
2021-03-01
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Online Access: | https://www.mdpi.com/2079-9292/10/7/805 |
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author | Shi Zuo Jianzhong Zhao Yumei Zhou |
author_facet | Shi Zuo Jianzhong Zhao Yumei Zhou |
author_sort | Shi Zuo |
collection | DOAJ |
description | This article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 <inline-formula>μ<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>W at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz. |
first_indexed | 2024-03-10T12:49:42Z |
format | Article |
id | doaj.art-d63b8a10cb6b45a996d1cc8f6975d57d |
institution | Directory Open Access Journal |
issn | 2079-9292 |
language | English |
last_indexed | 2024-03-10T12:49:42Z |
publishDate | 2021-03-01 |
publisher | MDPI AG |
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series | Electronics |
spelling | doaj.art-d63b8a10cb6b45a996d1cc8f6975d57d2023-11-21T13:12:54ZengMDPI AGElectronics2079-92922021-03-0110780510.3390/electronics10070805A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC SchemeShi Zuo0Jianzhong Zhao1Yumei Zhou2Institute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, ChinaInstitute of Microelectronics of the Chinese Academy of Sciences, Beijing 100029, ChinaThis article presents a low power digital controlled oscillator (DCO) with an ultra low power duty cycle correction (DCC) scheme. The DCO with the complementary cross-coupled topology uses the controllable tail resistor to improve the tail current efficiency. A robust duty cycle correction (DCC) scheme is introduced to replace self-biased inverters to save power further. The proposed DCO is implemented in a Semiconductor Manufacturing International Corporation (SMIC) 40 nm CMOS process. The measured phase noise at room temperature is −115 dBc/Hz at 1 MHz offset with a dissipation of 210 <inline-formula>μ<math xmlns="http://www.w3.org/1998/Math/MathML" display="inline"><semantics><mi mathvariant="sans-serif">μ</mi></semantics></math></inline-formula>W at an oscillating frequency of 2.12 GHz, and the resulin figure-of-merit is s −189 dBc/Hz.https://www.mdpi.com/2079-9292/10/7/805DCODCCultra low power |
spellingShingle | Shi Zuo Jianzhong Zhao Yumei Zhou A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme Electronics DCO DCC ultra low power |
title | A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme |
title_full | A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme |
title_fullStr | A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme |
title_full_unstemmed | A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme |
title_short | A 2.1 GHz, 210 μW, —189 dBc/Hz DCO with Ultra Low Power DCC Scheme |
title_sort | 2 1 ghz 210 μw 189 dbc hz dco with ultra low power dcc scheme |
topic | DCO DCC ultra low power |
url | https://www.mdpi.com/2079-9292/10/7/805 |
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