Flexible Software-Defined Packet Processing Using Low-Area Hardware
Computer networks are in the Software Defined Networking (SDN) and Network Function Virtualization (NFV) era. SDN brings a whole new set of flexibility and possibilities into the network. The data plane of forwarding devices can be programmed to provide functionality for any protocol, and to perform...
| Main Authors: | , , , , , |
|---|---|
| Format: | Article |
| Language: | English |
| Published: |
IEEE
2020-01-01
|
| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/9099029/ |
| _version_ | 1818608518051135488 |
|---|---|
| author | Hesam Zolfaghari Davide Rossi Walter Cerroni Hayate Okuhara Carla Raffaelli Jari Nurmi |
| author_facet | Hesam Zolfaghari Davide Rossi Walter Cerroni Hayate Okuhara Carla Raffaelli Jari Nurmi |
| author_sort | Hesam Zolfaghari |
| collection | DOAJ |
| description | Computer networks are in the Software Defined Networking (SDN) and Network Function Virtualization (NFV) era. SDN brings a whole new set of flexibility and possibilities into the network. The data plane of forwarding devices can be programmed to provide functionality for any protocol, and to perform novel network testing, diagnostics, and troubleshooting. One of the most dominant hardware architectures for implementing the programmable data plane is the Reconfigurable Match Tables (RMT) architecture. RMT's innovative programmable architecture enables support of novel networking protocols. However, there are certain shortcomings associated with its architecture that limit its scalability and lead to an unnecessarily complex architecture. In this paper, we present the details of an alternative packet parser and Match-Action pipeline. The parser sustains tenfold throughput at an area increase of only 32 percent. The pipeline supports unlimited combination of tables at minimum possible cost and provides a new level of flexibility to programmable Match-Action packet processing by allowing custom depth for actions. In addition, it has more advanced field-referencing mechanisms. Despite these architectural enhancements, it has 31 percent less area compared to RMT architecture. |
| first_indexed | 2024-12-16T14:43:55Z |
| format | Article |
| id | doaj.art-d7955665d6c94dbfaa96610e9debf89c |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-16T14:43:55Z |
| publishDate | 2020-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-d7955665d6c94dbfaa96610e9debf89c2022-12-21T22:27:50ZengIEEEIEEE Access2169-35362020-01-018989299894510.1109/ACCESS.2020.29966609099029Flexible Software-Defined Packet Processing Using Low-Area HardwareHesam Zolfaghari0https://orcid.org/0000-0002-0002-0525Davide Rossi1https://orcid.org/0000-0002-0651-5393Walter Cerroni2https://orcid.org/0000-0002-4629-031XHayate Okuhara3https://orcid.org/0000-0003-1582-0100Carla Raffaelli4https://orcid.org/0000-0002-1250-2476Jari Nurmi5https://orcid.org/0000-0003-2169-4606Electrical Engineering Unit, Tampere University, Tampere, FinlandDepartment of Electrical, Electronic, and Information Engineering, University of Bologna, Bologna, ItalyDepartment of Electrical, Electronic, and Information Engineering, University of Bologna, Bologna, ItalyDepartment of Electrical, Electronic, and Information Engineering, University of Bologna, Bologna, ItalyDepartment of Electrical, Electronic, and Information Engineering, University of Bologna, Bologna, ItalyElectrical Engineering Unit, Tampere University, Tampere, FinlandComputer networks are in the Software Defined Networking (SDN) and Network Function Virtualization (NFV) era. SDN brings a whole new set of flexibility and possibilities into the network. The data plane of forwarding devices can be programmed to provide functionality for any protocol, and to perform novel network testing, diagnostics, and troubleshooting. One of the most dominant hardware architectures for implementing the programmable data plane is the Reconfigurable Match Tables (RMT) architecture. RMT's innovative programmable architecture enables support of novel networking protocols. However, there are certain shortcomings associated with its architecture that limit its scalability and lead to an unnecessarily complex architecture. In this paper, we present the details of an alternative packet parser and Match-Action pipeline. The parser sustains tenfold throughput at an area increase of only 32 percent. The pipeline supports unlimited combination of tables at minimum possible cost and provides a new level of flexibility to programmable Match-Action packet processing by allowing custom depth for actions. In addition, it has more advanced field-referencing mechanisms. Despite these architectural enhancements, it has 31 percent less area compared to RMT architecture.https://ieeexplore.ieee.org/document/9099029/Software defined networkingprogrammable packet processinglow-area hardwareprogrammable data plane |
| spellingShingle | Hesam Zolfaghari Davide Rossi Walter Cerroni Hayate Okuhara Carla Raffaelli Jari Nurmi Flexible Software-Defined Packet Processing Using Low-Area Hardware IEEE Access Software defined networking programmable packet processing low-area hardware programmable data plane |
| title | Flexible Software-Defined Packet Processing Using Low-Area Hardware |
| title_full | Flexible Software-Defined Packet Processing Using Low-Area Hardware |
| title_fullStr | Flexible Software-Defined Packet Processing Using Low-Area Hardware |
| title_full_unstemmed | Flexible Software-Defined Packet Processing Using Low-Area Hardware |
| title_short | Flexible Software-Defined Packet Processing Using Low-Area Hardware |
| title_sort | flexible software defined packet processing using low area hardware |
| topic | Software defined networking programmable packet processing low-area hardware programmable data plane |
| url | https://ieeexplore.ieee.org/document/9099029/ |
| work_keys_str_mv | AT hesamzolfaghari flexiblesoftwaredefinedpacketprocessingusinglowareahardware AT daviderossi flexiblesoftwaredefinedpacketprocessingusinglowareahardware AT waltercerroni flexiblesoftwaredefinedpacketprocessingusinglowareahardware AT hayateokuhara flexiblesoftwaredefinedpacketprocessingusinglowareahardware AT carlaraffaelli flexiblesoftwaredefinedpacketprocessingusinglowareahardware AT jarinurmi flexiblesoftwaredefinedpacketprocessingusinglowareahardware |