Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer
Abstract Amorphous In–Ga–Zn-O (a-IGZO) thin-film transistor (TFT) memories are attracting many interests for future system-on-panel applications; however, they usually exhibit a poor erasing efficiency. In this article, we investigate voltage-polarity-dependent programming behaviors of an a-IGZO TFT...
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| Format: | Article |
| Language: | English |
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SpringerOpen
2019-12-01
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| Series: | Nanoscale Research Letters |
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| Online Access: | https://doi.org/10.1186/s11671-019-3204-7 |
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| author | Dan-Dan Liu Wen-Jun Liu Jun-Xiang Pei Lin-Yan Xie Jingyong Huo Xiaohan Wu Shi-Jin Ding |
| author_facet | Dan-Dan Liu Wen-Jun Liu Jun-Xiang Pei Lin-Yan Xie Jingyong Huo Xiaohan Wu Shi-Jin Ding |
| author_sort | Dan-Dan Liu |
| collection | DOAJ |
| description | Abstract Amorphous In–Ga–Zn-O (a-IGZO) thin-film transistor (TFT) memories are attracting many interests for future system-on-panel applications; however, they usually exhibit a poor erasing efficiency. In this article, we investigate voltage-polarity-dependent programming behaviors of an a-IGZO TFT memory with an atomic-layer-deposited ZnO charge trapping layer (CTL). The pristine devices demonstrate electrically programmable characteristics not only under positive gate biases but also under negative gate biases. In particular, the latter can generate a much higher programming efficiency than the former. Upon applying a gate bias pulse of +13 V/1 μs, the device shows a threshold voltage shift (ΔVth) of 2 V; and the ΔVth is as large as −6.5 V for a gate bias pulse of −13 V/1 μs. In the case of 12 V/1 ms programming (P) and −12 V/10 μs erasing (E), a memory window as large as 7.2 V can be achieved at 103 of P/E cycles. By comparing the ZnO CTLs annealed in O2 or N2 with the as-deposited one, it is concluded that the oxygen vacancy (VO)-related defects dominate the bipolar programming characteristics of the TFT memory devices. For programming at positive gate voltage, electrons are injected from the IGZO channel into the ZnO layer and preferentially trapped at deep levels of singly ionized oxygen vacancy (VO +) and doubly ionized oxygen vacancy (VO 2+). Regarding programming at negative gate voltage, electrons are de-trapped easily from neutral oxygen vacancies because of shallow donors and tunnel back to the channel. This thus leads to highly efficient erasing by the formation of additional ionized oxygen vacancies with positive charges. |
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| issn | 1931-7573 1556-276X |
| language | English |
| last_indexed | 2024-03-12T05:58:58Z |
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| series | Nanoscale Research Letters |
| spelling | doaj.art-d86e1be5300846afaece6fa461c5d3f52023-09-03T04:22:57ZengSpringerOpenNanoscale Research Letters1931-75731556-276X2019-12-011411810.1186/s11671-019-3204-7Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping LayerDan-Dan Liu0Wen-Jun Liu1Jun-Xiang Pei2Lin-Yan Xie3Jingyong Huo4Xiaohan Wu5Shi-Jin Ding6State Key Laboratory of ASIC and System, School of Microelectronics, Fudan UniversityState Key Laboratory of ASIC and System, School of Microelectronics, Fudan UniversityState Key Laboratory of ASIC and System, School of Microelectronics, Fudan UniversityState Key Laboratory of ASIC and System, School of Microelectronics, Fudan UniversityState Key Laboratory of ASIC and System, School of Microelectronics, Fudan UniversityState Key Laboratory of ASIC and System, School of Microelectronics, Fudan UniversityState Key Laboratory of ASIC and System, School of Microelectronics, Fudan UniversityAbstract Amorphous In–Ga–Zn-O (a-IGZO) thin-film transistor (TFT) memories are attracting many interests for future system-on-panel applications; however, they usually exhibit a poor erasing efficiency. In this article, we investigate voltage-polarity-dependent programming behaviors of an a-IGZO TFT memory with an atomic-layer-deposited ZnO charge trapping layer (CTL). The pristine devices demonstrate electrically programmable characteristics not only under positive gate biases but also under negative gate biases. In particular, the latter can generate a much higher programming efficiency than the former. Upon applying a gate bias pulse of +13 V/1 μs, the device shows a threshold voltage shift (ΔVth) of 2 V; and the ΔVth is as large as −6.5 V for a gate bias pulse of −13 V/1 μs. In the case of 12 V/1 ms programming (P) and −12 V/10 μs erasing (E), a memory window as large as 7.2 V can be achieved at 103 of P/E cycles. By comparing the ZnO CTLs annealed in O2 or N2 with the as-deposited one, it is concluded that the oxygen vacancy (VO)-related defects dominate the bipolar programming characteristics of the TFT memory devices. For programming at positive gate voltage, electrons are injected from the IGZO channel into the ZnO layer and preferentially trapped at deep levels of singly ionized oxygen vacancy (VO +) and doubly ionized oxygen vacancy (VO 2+). Regarding programming at negative gate voltage, electrons are de-trapped easily from neutral oxygen vacancies because of shallow donors and tunnel back to the channel. This thus leads to highly efficient erasing by the formation of additional ionized oxygen vacancies with positive charges.https://doi.org/10.1186/s11671-019-3204-7ZnOIn–Ga–Zn–ONonvolatile memoryThin-film transistor (TFT)Oxygen vacancy |
| spellingShingle | Dan-Dan Liu Wen-Jun Liu Jun-Xiang Pei Lin-Yan Xie Jingyong Huo Xiaohan Wu Shi-Jin Ding Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer Nanoscale Research Letters ZnO In–Ga–Zn–O Nonvolatile memory Thin-film transistor (TFT) Oxygen vacancy |
| title | Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer |
| title_full | Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer |
| title_fullStr | Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer |
| title_full_unstemmed | Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer |
| title_short | Voltage-Polarity Dependent Programming Behaviors of Amorphous In–Ga–Zn–O Thin-Film Transistor Memory with an Atomic-Layer-Deposited ZnO Charge Trapping Layer |
| title_sort | voltage polarity dependent programming behaviors of amorphous in ga zn o thin film transistor memory with an atomic layer deposited zno charge trapping layer |
| topic | ZnO In–Ga–Zn–O Nonvolatile memory Thin-film transistor (TFT) Oxygen vacancy |
| url | https://doi.org/10.1186/s11671-019-3204-7 |
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