A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm
Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on component...
| Main Authors: | , , , , , , , , , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2019-02-01
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| Series: | Journal of Low Power Electronics and Applications |
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| Online Access: | https://www.mdpi.com/2079-9268/9/1/8 |
| _version_ | 1798004887048421376 |
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| author | Jean-Frédéric Christmann Florent Berthier David Coriat Ivan Miro-Panades Eric Guthmuller Sébastien Thuries Yvain Thonnart Adam Makosiej Olivier Debicki Frédéric Heitzmann Alexandre Valentian Pascal Vivet Edith Beigné |
| author_facet | Jean-Frédéric Christmann Florent Berthier David Coriat Ivan Miro-Panades Eric Guthmuller Sébastien Thuries Yvain Thonnart Adam Makosiej Olivier Debicki Frédéric Heitzmann Alexandre Valentian Pascal Vivet Edith Beigné |
| author_sort | Jean-Frédéric Christmann |
| collection | DOAJ |
| description | Due to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 ns@9.2 Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm. |
| first_indexed | 2024-04-11T12:30:34Z |
| format | Article |
| id | doaj.art-d8d0d3d329684d829649a10e2a06f695 |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-11T12:30:34Z |
| publishDate | 2019-02-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-d8d0d3d329684d829649a10e2a06f6952022-12-22T04:23:46ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682019-02-0191810.3390/jlpea9010008jlpea9010008A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nmJean-Frédéric Christmann0Florent Berthier1David Coriat2Ivan Miro-Panades3Eric Guthmuller4Sébastien Thuries5Yvain Thonnart6Adam Makosiej7Olivier Debicki8Frédéric Heitzmann9Alexandre Valentian10Pascal Vivet11Edith Beigné12CEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceCEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceCEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceCEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceCEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceCEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceCEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceCEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceCEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceCEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceCEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceCEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceCEA, LETI, MINATEC Campus, F-38054 Grenoble, FranceDue to low activity in Internet of Things (IoT) applications, systems tend to leverage low power modes in order to reduce their power consumption. Normally-off computing thus arose, consisting in having turned off most part of a system’s power supply, while dynamically turning on components as the application needs it. As wake up sources may be diverse, simple controllers are integrated to handle smart wake up schemes. Therefore, to prevent overconsumption while transitioning to running mode, fast wake up sequences are required. An asynchronous 16-bit Reduced Instruction Set Computer (RISC) Wake-up Controller (WuC) is proposed demonstrating 50.5 ns@9.2 Million Instructions Per Second (MIPS)@0.6 V wake-up latency, drastically reducing the overall wake-up energy of IoT systems. A clockless implementation of the controller saves the booting time and the power consumption of a clock generator, while providing high robustness to environmental variations such as supply voltage level. The WuC is also able to run simple tasks with a reduced Instruction Set Architecture (ISA) and achieves as low as 11.2 pJ/inst @0.5 V in Fully Depleted Silicon On Insulator (FDSOI) 28 nm.https://www.mdpi.com/2079-9268/9/1/8wake-up controllerIoTQDI asynchronous logicnormally-off computingbig/little architecture |
| spellingShingle | Jean-Frédéric Christmann Florent Berthier David Coriat Ivan Miro-Panades Eric Guthmuller Sébastien Thuries Yvain Thonnart Adam Makosiej Olivier Debicki Frédéric Heitzmann Alexandre Valentian Pascal Vivet Edith Beigné A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm Journal of Low Power Electronics and Applications wake-up controller IoT QDI asynchronous logic normally-off computing big/little architecture |
| title | A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm |
| title_full | A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm |
| title_fullStr | A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm |
| title_full_unstemmed | A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm |
| title_short | A 50.5 ns Wake-Up-Latency 11.2 pJ/Inst Asynchronous Wake-Up Controller in FDSOI 28 nm |
| title_sort | 50 5 ns wake up latency 11 2 pj inst asynchronous wake up controller in fdsoi 28 nm |
| topic | wake-up controller IoT QDI asynchronous logic normally-off computing big/little architecture |
| url | https://www.mdpi.com/2079-9268/9/1/8 |
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