SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform
This paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processi...
| Main Authors: | , , , , |
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| Format: | Article |
| Language: | English |
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MDPI AG
2018-01-01
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| Series: | Journal of Low Power Electronics and Applications |
| Subjects: | |
| Online Access: | http://www.mdpi.com/2079-9268/8/1/1 |
| _version_ | 1798039483591950336 |
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| author | Maher Jridi Thibault Chapel Victor Dorez Guénolé Le Bougeant Antoine Le Botlan |
| author_facet | Maher Jridi Thibault Chapel Victor Dorez Guénolé Le Bougeant Antoine Le Botlan |
| author_sort | Maher Jridi |
| collection | DOAJ |
| description | This paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processing due to cloud latency and privacy concerns. With edge computing, data are processed, analyzed, and encrypted very close to the device, which enable the ability to secure data and act rapidly on connected things. The proposed edge computing system is composed of a reconfigurable module to simultaneously compress and encrypt multiple images, along with wireless image transmission and display functionalities. A lightweight implementation of the proposed design is obtained by approximate computing of the discrete cosine transform (DCT) and by using a simple chaotic generator which greatly enhances the encryption efficiency. The deployed solution includes four configurations based on HW/SW partitioning in order to handle the compromise between execution time, area, and energy consumption. It was found with the experimental setup that by moving more components to hardware execution, a timing speedup of more than nine times could be achieved with a negligible amount of energy consumption. The power efficiency was then enhanced by a ratio of 7.7 times. |
| first_indexed | 2024-04-11T21:54:31Z |
| format | Article |
| id | doaj.art-d9595698a9ef4409882b91d108e07282 |
| institution | Directory Open Access Journal |
| issn | 2079-9268 |
| language | English |
| last_indexed | 2024-04-11T21:54:31Z |
| publishDate | 2018-01-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Journal of Low Power Electronics and Applications |
| spelling | doaj.art-d9595698a9ef4409882b91d108e072822022-12-22T04:01:09ZengMDPI AGJournal of Low Power Electronics and Applications2079-92682018-01-0181110.3390/jlpea8010001jlpea8010001SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental PlatformMaher Jridi0Thibault Chapel1Victor Dorez2Guénolé Le Bougeant3Antoine Le Botlan4ISEN Yncrea Ouest, VISION Team, 20 rue Cuirassée Bretagne, 29200 Brest, FranceISEN Yncrea Ouest, VISION Team, 20 rue Cuirassée Bretagne, 29200 Brest, FranceISEN Yncrea Ouest, VISION Team, 20 rue Cuirassée Bretagne, 29200 Brest, FranceISEN Yncrea Ouest, VISION Team, 20 rue Cuirassée Bretagne, 29200 Brest, FranceISEN Yncrea Ouest, VISION Team, 20 rue Cuirassée Bretagne, 29200 Brest, FranceThis paper presents an algorithm/architecture and Hardware/Software co-designs for implementing a digital edge computing layer on a Zynq platform in the context of the Internet of Multimedia Things (IoMT). Traditional cloud computing is no longer suitable for applications that require image processing due to cloud latency and privacy concerns. With edge computing, data are processed, analyzed, and encrypted very close to the device, which enable the ability to secure data and act rapidly on connected things. The proposed edge computing system is composed of a reconfigurable module to simultaneously compress and encrypt multiple images, along with wireless image transmission and display functionalities. A lightweight implementation of the proposed design is obtained by approximate computing of the discrete cosine transform (DCT) and by using a simple chaotic generator which greatly enhances the encryption efficiency. The deployed solution includes four configurations based on HW/SW partitioning in order to handle the compromise between execution time, area, and energy consumption. It was found with the experimental setup that by moving more components to hardware execution, a timing speedup of more than nine times could be achieved with a negligible amount of energy consumption. The power efficiency was then enhanced by a ratio of 7.7 times.http://www.mdpi.com/2079-9268/8/1/1Internet of Multimedia Thingspower efficiencyadaptive signal processingapproximate computingFPGA design |
| spellingShingle | Maher Jridi Thibault Chapel Victor Dorez Guénolé Le Bougeant Antoine Le Botlan SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform Journal of Low Power Electronics and Applications Internet of Multimedia Things power efficiency adaptive signal processing approximate computing FPGA design |
| title | SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform |
| title_full | SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform |
| title_fullStr | SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform |
| title_full_unstemmed | SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform |
| title_short | SoC-Based Edge Computing Gateway in the Context of the Internet of Multimedia Things: Experimental Platform |
| title_sort | soc based edge computing gateway in the context of the internet of multimedia things experimental platform |
| topic | Internet of Multimedia Things power efficiency adaptive signal processing approximate computing FPGA design |
| url | http://www.mdpi.com/2079-9268/8/1/1 |
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