An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memories
In this work we experimentally demonstrate a Si _3 N _4 photonic integrated circuit which offers row decoding and RAM addressing functionalities. The passive integrated structure comprises a MRR-based wavelength filtering bank scheme in a 2 × 4 configuration, which reveals a suppression ratio in the...
| Main Authors: | , , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IOP Publishing
2023-01-01
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| Series: | JPhys Photonics |
| Subjects: | |
| Online Access: | https://doi.org/10.1088/2515-7647/acf973 |
| _version_ | 1797667803843526656 |
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| author | S Simos T Moschos K Fotiadis D Chatzitheocharis T Alexoudi C Vagionas D Sacchetto M Zervas N Pleros |
| author_facet | S Simos T Moschos K Fotiadis D Chatzitheocharis T Alexoudi C Vagionas D Sacchetto M Zervas N Pleros |
| author_sort | S Simos |
| collection | DOAJ |
| description | In this work we experimentally demonstrate a Si _3 N _4 photonic integrated circuit which offers row decoding and RAM addressing functionalities. The passive integrated structure comprises a MRR-based wavelength filtering bank scheme in a 2 × 4 configuration, which reveals a suppression ratio in the range of 12–25 dB. The performance of the optical circuit has been evaluated in a system-level testbed, where successful addressing in one RAM row has been achieved. Error-free operation has been accomplished for all cases under study, with the whole row decoder system’s performance to offer a total power penalty of 2.5 dB. |
| first_indexed | 2024-03-11T20:19:50Z |
| format | Article |
| id | doaj.art-d9ccec65d910419fb27515de523f14f1 |
| institution | Directory Open Access Journal |
| issn | 2515-7647 |
| language | English |
| last_indexed | 2024-03-11T20:19:50Z |
| publishDate | 2023-01-01 |
| publisher | IOP Publishing |
| record_format | Article |
| series | JPhys Photonics |
| spelling | doaj.art-d9ccec65d910419fb27515de523f14f12023-10-03T09:30:24ZengIOP PublishingJPhys Photonics2515-76472023-01-015404500210.1088/2515-7647/acf973An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memoriesS Simos0https://orcid.org/0000-0002-0776-3532T Moschos1K Fotiadis2D Chatzitheocharis3T Alexoudi4https://orcid.org/0000-0001-6722-201XC Vagionas5D Sacchetto6M Zervas7N Pleros8Department of Informatics, Aristotle University of Thessaloniki , Thessaloniki 54124, Greece; Centre for Interdisciplinary Research and Innovation, Aristotle University of Thessaloniki , Thessaloniki 52124, GreeceDepartment of Informatics, Aristotle University of Thessaloniki , Thessaloniki 54124, Greece; Centre for Interdisciplinary Research and Innovation, Aristotle University of Thessaloniki , Thessaloniki 52124, GreeceDepartment of Informatics, Aristotle University of Thessaloniki , Thessaloniki 54124, Greece; Centre for Interdisciplinary Research and Innovation, Aristotle University of Thessaloniki , Thessaloniki 52124, GreeceCentre for Interdisciplinary Research and Innovation, Aristotle University of Thessaloniki , Thessaloniki 52124, Greece; School of Physics, Aristotle University of Thessaloniki , Thessaloniki 54124, GreeceDepartment of Informatics, Aristotle University of Thessaloniki , Thessaloniki 54124, Greece; Centre for Interdisciplinary Research and Innovation, Aristotle University of Thessaloniki , Thessaloniki 52124, GreeceDepartment of Informatics, Aristotle University of Thessaloniki , Thessaloniki 54124, Greece; Centre for Interdisciplinary Research and Innovation, Aristotle University of Thessaloniki , Thessaloniki 52124, GreeceLIGENTEC SA, Chemin de la Dent-d’Oche 1B , 1024 Ecublens, SwitzerlandLIGENTEC SA, Chemin de la Dent-d’Oche 1B , 1024 Ecublens, SwitzerlandDepartment of Informatics, Aristotle University of Thessaloniki , Thessaloniki 54124, Greece; Centre for Interdisciplinary Research and Innovation, Aristotle University of Thessaloniki , Thessaloniki 52124, GreeceIn this work we experimentally demonstrate a Si _3 N _4 photonic integrated circuit which offers row decoding and RAM addressing functionalities. The passive integrated structure comprises a MRR-based wavelength filtering bank scheme in a 2 × 4 configuration, which reveals a suppression ratio in the range of 12–25 dB. The performance of the optical circuit has been evaluated in a system-level testbed, where successful addressing in one RAM row has been achieved. Error-free operation has been accomplished for all cases under study, with the whole row decoder system’s performance to offer a total power penalty of 2.5 dB.https://doi.org/10.1088/2515-7647/acf973optical RAMoptical row decoderintegrated photonic circuit |
| spellingShingle | S Simos T Moschos K Fotiadis D Chatzitheocharis T Alexoudi C Vagionas D Sacchetto M Zervas N Pleros An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memories JPhys Photonics optical RAM optical row decoder integrated photonic circuit |
| title | An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memories |
| title_full | An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memories |
| title_fullStr | An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memories |
| title_full_unstemmed | An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memories |
| title_short | An all-passive Si3N4 optical row decoder circuit for addressable optical RAM memories |
| title_sort | all passive si3n4 optical row decoder circuit for addressable optical ram memories |
| topic | optical RAM optical row decoder integrated photonic circuit |
| url | https://doi.org/10.1088/2515-7647/acf973 |
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