CNTFET-based SRAM cell design using INDEP technique
As the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube f...
| Main Authors: | , , |
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| Format: | Article |
| Language: | English |
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Elsevier
2024-03-01
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| Series: | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
| Subjects: | |
| Online Access: | http://www.sciencedirect.com/science/article/pii/S2772671124000597 |
| _version_ | 1797256306760876032 |
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| author | Mehwish Maqbool Vijay Kumar Sharma Neeraj Kaushik |
| author_facet | Mehwish Maqbool Vijay Kumar Sharma Neeraj Kaushik |
| author_sort | Mehwish Maqbool |
| collection | DOAJ |
| description | As the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube field effect transistor (CNTFET) has exhibited remarkable advantages compared to MOSFETs in circuit designs within the nanoscale range, owing to its extraordinary characteristics. In this work, a CNTFET-based six-transistor (6T) static random access memory (SRAM) cell is designed using the low power input-dependent (INDEP) technique. The suggested circuits' performance and efficiency is enhanced using CNTFET technology. The suggested design undergoes circuit simulations using the 32 nm CNTFET Stanford model. The results obtained from the simulations indicate that the suggested INDEP 6T SRAM cell surpasses both the conventional 6T SRAM cell and the previous designs in terms of power dissipation, delay, and energy efficiency. The hold, read, and write operations use less power, and the hold and write operations take less time to complete. The suggested design also demonstrates improved energy efficiency for hold and read operations compared to the conventional design. Furthermore, a stability analysis is conducted on the suggested INDEP 6T SRAM cell using the static noise margin (SNM) metric. The suggested INDEP approach in comparison to the other schemes has greater SNMs for hold, write, and read operations, indicating improved SRAM cell stability. |
| first_indexed | 2024-03-07T20:03:33Z |
| format | Article |
| id | doaj.art-db3626e3363f404cac0a16ae7293d6fe |
| institution | Directory Open Access Journal |
| issn | 2772-6711 |
| language | English |
| last_indexed | 2024-04-24T22:19:39Z |
| publishDate | 2024-03-01 |
| publisher | Elsevier |
| record_format | Article |
| series | e-Prime: Advances in Electrical Engineering, Electronics and Energy |
| spelling | doaj.art-db3626e3363f404cac0a16ae7293d6fe2024-03-20T06:12:01ZengElseviere-Prime: Advances in Electrical Engineering, Electronics and Energy2772-67112024-03-017100477CNTFET-based SRAM cell design using INDEP techniqueMehwish Maqbool0Vijay Kumar Sharma1Neeraj Kaushik2School of Electronics and Communication Engineering, Shri Mata Vaishno Devi University, Katra, IndiaSchool of Electronics and Communication Engineering, Shri Mata Vaishno Devi University, Katra, India; Corresponding author.Department of Electronics & Communication Engineering, Teerthanker Mahaveer University Moradabad, IndiaAs the size of the transistor decreases in the nanoscale regime, certain parameters, such as, cell stability, power dissipation, and delay, have changed. This poses a significant challenge when attempting to scale down metal oxide semiconductor field effect transistor (MOSFET). The carbon nanotube field effect transistor (CNTFET) has exhibited remarkable advantages compared to MOSFETs in circuit designs within the nanoscale range, owing to its extraordinary characteristics. In this work, a CNTFET-based six-transistor (6T) static random access memory (SRAM) cell is designed using the low power input-dependent (INDEP) technique. The suggested circuits' performance and efficiency is enhanced using CNTFET technology. The suggested design undergoes circuit simulations using the 32 nm CNTFET Stanford model. The results obtained from the simulations indicate that the suggested INDEP 6T SRAM cell surpasses both the conventional 6T SRAM cell and the previous designs in terms of power dissipation, delay, and energy efficiency. The hold, read, and write operations use less power, and the hold and write operations take less time to complete. The suggested design also demonstrates improved energy efficiency for hold and read operations compared to the conventional design. Furthermore, a stability analysis is conducted on the suggested INDEP 6T SRAM cell using the static noise margin (SNM) metric. The suggested INDEP approach in comparison to the other schemes has greater SNMs for hold, write, and read operations, indicating improved SRAM cell stability.http://www.sciencedirect.com/science/article/pii/S2772671124000597SRAMCNTFETSNMINDEPVLSICNT |
| spellingShingle | Mehwish Maqbool Vijay Kumar Sharma Neeraj Kaushik CNTFET-based SRAM cell design using INDEP technique e-Prime: Advances in Electrical Engineering, Electronics and Energy SRAM CNTFET SNM INDEP VLSI CNT |
| title | CNTFET-based SRAM cell design using INDEP technique |
| title_full | CNTFET-based SRAM cell design using INDEP technique |
| title_fullStr | CNTFET-based SRAM cell design using INDEP technique |
| title_full_unstemmed | CNTFET-based SRAM cell design using INDEP technique |
| title_short | CNTFET-based SRAM cell design using INDEP technique |
| title_sort | cntfet based sram cell design using indep technique |
| topic | SRAM CNTFET SNM INDEP VLSI CNT |
| url | http://www.sciencedirect.com/science/article/pii/S2772671124000597 |
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