Parallel synaptic design of ferroelectric tunnel junctions for neuromorphic computing
We propose a novel synaptic design of more efficient neuromorphic edge-computing with substantially improved linearity and extremely low variability. Specifically, a parallel arrangement of ferroelectric tunnel junctions (FTJ) with an incremental pulsing scheme provides a great improvement in linear...
| Main Authors: | , , , , , , , , , |
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| Format: | Article |
| Language: | English |
| Published: |
IOP Publishing
2023-01-01
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| Series: | Neuromorphic Computing and Engineering |
| Subjects: | |
| Online Access: | https://doi.org/10.1088/2634-4386/accc51 |
| _version_ | 1797661953202585600 |
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| author | Taehwan Moon Hyun Jae Lee Seunggeol Nam Hagyoul Bae Duk-Hyun Choe Sanghyun Jo Yun Seong Lee Yoonsang Park J Joshua Yang Jinseong Heo |
| author_facet | Taehwan Moon Hyun Jae Lee Seunggeol Nam Hagyoul Bae Duk-Hyun Choe Sanghyun Jo Yun Seong Lee Yoonsang Park J Joshua Yang Jinseong Heo |
| author_sort | Taehwan Moon |
| collection | DOAJ |
| description | We propose a novel synaptic design of more efficient neuromorphic edge-computing with substantially improved linearity and extremely low variability. Specifically, a parallel arrangement of ferroelectric tunnel junctions (FTJ) with an incremental pulsing scheme provides a great improvement in linearity for synaptic weight updating by averaging weight update rates of multiple devices. To enable such design with FTJ building blocks, we have demonstrated the lowest reported variability: σ / μ = 0.036 for cycle to cycle and σ / μ = 0.032 for device among six dies across an 8 inch wafer. With such devices, we further show improved synaptic performance and pattern recognition accuracy through experiments combined with simulations. |
| first_indexed | 2024-03-11T18:53:03Z |
| format | Article |
| id | doaj.art-db5675976ec94bde8fc43525d5ede6de |
| institution | Directory Open Access Journal |
| issn | 2634-4386 |
| language | English |
| last_indexed | 2024-03-11T18:53:03Z |
| publishDate | 2023-01-01 |
| publisher | IOP Publishing |
| record_format | Article |
| series | Neuromorphic Computing and Engineering |
| spelling | doaj.art-db5675976ec94bde8fc43525d5ede6de2023-10-11T08:46:49ZengIOP PublishingNeuromorphic Computing and Engineering2634-43862023-01-013202400110.1088/2634-4386/accc51Parallel synaptic design of ferroelectric tunnel junctions for neuromorphic computingTaehwan Moon0https://orcid.org/0000-0003-1197-6677Hyun Jae Lee1Seunggeol Nam2Hagyoul Bae3Duk-Hyun Choe4Sanghyun Jo5Yun Seong Lee6Yoonsang Park7J Joshua Yang8https://orcid.org/0000-0001-8242-7531Jinseong Heo9Beyond Silicon Lab, Samsung Advanced Institute of Technology, Samsung Electronics , Suwon, Gyeonggi-do, Republic of Korea; Department of Electrical and Computer Engineering, University of Southern California , Los Angeles, CA, United States of AmericaBeyond Silicon Lab, Samsung Advanced Institute of Technology, Samsung Electronics , Suwon, Gyeonggi-do, Republic of KoreaBeyond Silicon Lab, Samsung Advanced Institute of Technology, Samsung Electronics , Suwon, Gyeonggi-do, Republic of KoreaBeyond Silicon Lab, Samsung Advanced Institute of Technology, Samsung Electronics , Suwon, Gyeonggi-do, Republic of Korea; Department of Electronic Engineering, Jeonbuk National University , Jeonju, Jeollabuk-do, Republic of KoreaBeyond Silicon Lab, Samsung Advanced Institute of Technology, Samsung Electronics , Suwon, Gyeonggi-do, Republic of KoreaBeyond Silicon Lab, Samsung Advanced Institute of Technology, Samsung Electronics , Suwon, Gyeonggi-do, Republic of KoreaBeyond Silicon Lab, Samsung Advanced Institute of Technology, Samsung Electronics , Suwon, Gyeonggi-do, Republic of KoreaBeyond Silicon Lab, Samsung Advanced Institute of Technology, Samsung Electronics , Suwon, Gyeonggi-do, Republic of KoreaDepartment of Electrical and Computer Engineering, University of Southern California , Los Angeles, CA, United States of AmericaBeyond Silicon Lab, Samsung Advanced Institute of Technology, Samsung Electronics , Suwon, Gyeonggi-do, Republic of KoreaWe propose a novel synaptic design of more efficient neuromorphic edge-computing with substantially improved linearity and extremely low variability. Specifically, a parallel arrangement of ferroelectric tunnel junctions (FTJ) with an incremental pulsing scheme provides a great improvement in linearity for synaptic weight updating by averaging weight update rates of multiple devices. To enable such design with FTJ building blocks, we have demonstrated the lowest reported variability: σ / μ = 0.036 for cycle to cycle and σ / μ = 0.032 for device among six dies across an 8 inch wafer. With such devices, we further show improved synaptic performance and pattern recognition accuracy through experiments combined with simulations.https://doi.org/10.1088/2634-4386/accc51artificial synapseferroelectric tunnel junctionhafnium oxide |
| spellingShingle | Taehwan Moon Hyun Jae Lee Seunggeol Nam Hagyoul Bae Duk-Hyun Choe Sanghyun Jo Yun Seong Lee Yoonsang Park J Joshua Yang Jinseong Heo Parallel synaptic design of ferroelectric tunnel junctions for neuromorphic computing Neuromorphic Computing and Engineering artificial synapse ferroelectric tunnel junction hafnium oxide |
| title | Parallel synaptic design of ferroelectric tunnel junctions for neuromorphic computing |
| title_full | Parallel synaptic design of ferroelectric tunnel junctions for neuromorphic computing |
| title_fullStr | Parallel synaptic design of ferroelectric tunnel junctions for neuromorphic computing |
| title_full_unstemmed | Parallel synaptic design of ferroelectric tunnel junctions for neuromorphic computing |
| title_short | Parallel synaptic design of ferroelectric tunnel junctions for neuromorphic computing |
| title_sort | parallel synaptic design of ferroelectric tunnel junctions for neuromorphic computing |
| topic | artificial synapse ferroelectric tunnel junction hafnium oxide |
| url | https://doi.org/10.1088/2634-4386/accc51 |
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