Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count
Voltage source Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications due to their advantages like modularity and better power quality. However, the number of components used is significant. In this paper, an improved asymmetrical multilevel inverter topology...
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IEEE
2021-01-01
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| Series: | IEEE Access |
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| Online Access: | https://ieeexplore.ieee.org/document/9424556/ |
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| author | M. Saad Bin Arif Uvais Mustafa Shahrin Bin Md Ayob Jose Rodriguez Abdul Nadeem Mohamed Abdelrahem |
| author_facet | M. Saad Bin Arif Uvais Mustafa Shahrin Bin Md Ayob Jose Rodriguez Abdul Nadeem Mohamed Abdelrahem |
| author_sort | M. Saad Bin Arif |
| collection | DOAJ |
| description | Voltage source Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications due to their advantages like modularity and better power quality. However, the number of components used is significant. In this paper, an improved asymmetrical multilevel inverter topology is proposed producing 17-levels output voltage utilizing two dc sources. The circuit is developed to reduce the number of isolated dc-sources used without reducing output levels. The circuit utilizes six two-quadrant switches, three four-quadrant switches and four capacitors. The capacitors are self-balancing and do not require extra attention, i.e. the control system is simple for the proposed MLI. Detailed analysis of the topology under linear and non-linear loading conditions is carried out. Comparison with other similar topologies shows that the proposed topology is superior in device count, power quality, Total Standing Voltage (TSV), and cost factor. The performance of the topology is validated for different load conditions through MATLAB/Simulink environment and the prototype developed in the laboratory. Furthermore, thermal analysis of the circuit is done, and the losses are calculated via PLECS software. The topology offers a total harmonic distortion (THD) of 4.79% in the output voltage, with all the lower order harmonics being less than 5% complying with the IEEE standards. |
| first_indexed | 2024-12-16T12:53:01Z |
| format | Article |
| id | doaj.art-db7e9b7fa29d4c33bf8fec6d40b1d84c |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-16T12:53:01Z |
| publishDate | 2021-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-db7e9b7fa29d4c33bf8fec6d40b1d84c2022-12-21T22:31:06ZengIEEEIEEE Access2169-35362021-01-019697106972310.1109/ACCESS.2021.30779689424556Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device CountM. Saad Bin Arif0https://orcid.org/0000-0002-6450-4940Uvais Mustafa1Shahrin Bin Md Ayob2https://orcid.org/0000-0003-0465-9657Jose Rodriguez3https://orcid.org/0000-0002-1410-4121Abdul Nadeem4https://orcid.org/0000-0002-5168-4364Mohamed Abdelrahem5https://orcid.org/0000-0003-2923-2094Department of Electrical Engineering, Zakir Husain College of Engineering and Technology, Aligarh Muslim University, Aligarh, IndiaDepartment of Electrical Engineering, Zakir Husain College of Engineering and Technology, Aligarh Muslim University, Aligarh, IndiaPower Engineering Department, School of Electrical Engineering, Universiti Teknologi Malaysia (UTM), Johor, MalaysiaDepartment of Engineering Sciences, Universidad Andres Bello, Santiago, ChileDepartment of Electrical Engineering, Zakir Husain College of Engineering and Technology, Aligarh Muslim University, Aligarh, IndiaChair of Electrical Drive Systems and Power Electronics (EAL), Technische Universität München, München, GermanyVoltage source Multilevel Inverters (MLIs) are vital components for medium voltage and high-power applications due to their advantages like modularity and better power quality. However, the number of components used is significant. In this paper, an improved asymmetrical multilevel inverter topology is proposed producing 17-levels output voltage utilizing two dc sources. The circuit is developed to reduce the number of isolated dc-sources used without reducing output levels. The circuit utilizes six two-quadrant switches, three four-quadrant switches and four capacitors. The capacitors are self-balancing and do not require extra attention, i.e. the control system is simple for the proposed MLI. Detailed analysis of the topology under linear and non-linear loading conditions is carried out. Comparison with other similar topologies shows that the proposed topology is superior in device count, power quality, Total Standing Voltage (TSV), and cost factor. The performance of the topology is validated for different load conditions through MATLAB/Simulink environment and the prototype developed in the laboratory. Furthermore, thermal analysis of the circuit is done, and the losses are calculated via PLECS software. The topology offers a total harmonic distortion (THD) of 4.79% in the output voltage, with all the lower order harmonics being less than 5% complying with the IEEE standards.https://ieeexplore.ieee.org/document/9424556/Asymmetrical convertersmultilevel inverter (MLI)reduced device counttotal standing voltage (TSV)nearest level control (NLC) |
| spellingShingle | M. Saad Bin Arif Uvais Mustafa Shahrin Bin Md Ayob Jose Rodriguez Abdul Nadeem Mohamed Abdelrahem Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count IEEE Access Asymmetrical converters multilevel inverter (MLI) reduced device count total standing voltage (TSV) nearest level control (NLC) |
| title | Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count |
| title_full | Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count |
| title_fullStr | Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count |
| title_full_unstemmed | Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count |
| title_short | Asymmetrical 17-Level Inverter Topology With Reduced Total Standing Voltage and Device Count |
| title_sort | asymmetrical 17 level inverter topology with reduced total standing voltage and device count |
| topic | Asymmetrical converters multilevel inverter (MLI) reduced device count total standing voltage (TSV) nearest level control (NLC) |
| url | https://ieeexplore.ieee.org/document/9424556/ |
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