Ternary combinational logic gate design based on tri-valued memristors
Traditional binary combinational logic circuits are generally obtained by cascading multiple basic logic gate circuits, using more components and complicated wiring. In contrast to the binary logic circuit design in this method, ternary combinational logic circuit implementation is more complicated....
Main Authors: | Xiao-Jing Li, Xiao-Yuan Wang, Pu Li, Herbert H. C. Iu, Zhi-Qun Cheng |
---|---|
Format: | Article |
Language: | English |
Published: |
Frontiers Media S.A.
2023-10-01
|
Series: | Frontiers in Physics |
Subjects: | |
Online Access: | https://www.frontiersin.org/articles/10.3389/fphy.2023.1292336/full |
Similar Items
-
Design and Simulation of Balanced Ternary Priority Encoder
by: Aadarsh Ganesh Goenka, et al.
Published: (2024-08-01) -
Noise tolerant and power optimized ternary combinational circuits for arithmetic logic unit
by: Katyayani Chauhan, et al.
Published: (2025-03-01) -
TERNARY ∗-BANDS ARE GLOBALLY DETERMINED
by: Indrani Dutta, et al.
Published: (2023-07-01) -
Ternary encoder and decoder designs in RRAM and CNTFET technologies
by: Shams Ul Haq, et al.
Published: (2024-03-01) -
Analog models for ternary combinational logic elements
by: Semenov, Andrey Andreevich, et al.
Published: (2024-12-01)