Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs
The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed...
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MDPI AG
2020-09-01
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| Series: | Micromachines |
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| Online Access: | https://www.mdpi.com/2072-666X/11/10/887 |
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| author | Tae Jun Ahn Yun Seop Yu |
| author_facet | Tae Jun Ahn Yun Seop Yu |
| author_sort | Tae Jun Ahn |
| collection | DOAJ |
| description | The junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET. |
| first_indexed | 2024-03-10T16:06:03Z |
| format | Article |
| id | doaj.art-ddee3ebf8a024be5bf888d40f9fa12a1 |
| institution | Directory Open Access Journal |
| issn | 2072-666X |
| language | English |
| last_indexed | 2024-03-10T16:06:03Z |
| publishDate | 2020-09-01 |
| publisher | MDPI AG |
| record_format | Article |
| series | Micromachines |
| spelling | doaj.art-ddee3ebf8a024be5bf888d40f9fa12a12023-11-20T14:55:41ZengMDPI AGMicromachines2072-666X2020-09-01111088710.3390/mi11100887Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETsTae Jun Ahn0Yun Seop Yu1Department of Electrical, Electronic and Control Engineering and IITC, Hankyong National University, 327 Jungang-ro, Anseong-si, Gyenggi-do 17579, KoreaDepartment of Electrical, Electronic and Control Engineering and IITC, Hankyong National University, 327 Jungang-ro, Anseong-si, Gyenggi-do 17579, KoreaThe junctionless field-effect transistor (JLFET) compact model using the model parameters extracted from the LETI-UTSOI (version 2.1) model was proposed to perform circuit simulation considering the electrical coupling between the stacked JLFETs of a monolithic 3D integrated circuit (M3DIC) composed of JLFETs (M3DIC-JLFET). We validated the model by extracting the model parameters and comparing the simulation results of the technology computer-aided design and the Synopsys HSPICE circuit simulator. The performance of the M3DIC-JLFET was compared with that of the M3DIC composed of MOSFETs (M3DIC-MOSFET). The performance of a fan-out-3 ring oscillator with M3DIC-JLFET varied by less than 3% compared to that with M3DIC-MOSFET. The performances of ring oscillators of M3DIC-JLFET and M3DIC-MOSFET were almost the same. We simulated the performances of M3DICs such as an inverter, a NAND, a NOR, a 2 × 1 multiplexer, and a D flip-flop. The overall performance of the M3DIC-MOSFET was slightly better than that of the M3DIC-JLFET.https://www.mdpi.com/2072-666X/11/10/887junctionless FETJLFETelectrical couplingcircuit simulationparameter extractionmonolithic 3D integrated circuit (IC) |
| spellingShingle | Tae Jun Ahn Yun Seop Yu Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs Micromachines junctionless FET JLFET electrical coupling circuit simulation parameter extraction monolithic 3D integrated circuit (IC) |
| title | Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs |
| title_full | Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs |
| title_fullStr | Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs |
| title_full_unstemmed | Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs |
| title_short | Circuit Simulation Considering Electrical Coupling in Monolithic 3D Logics with Junctionless FETs |
| title_sort | circuit simulation considering electrical coupling in monolithic 3d logics with junctionless fets |
| topic | junctionless FET JLFET electrical coupling circuit simulation parameter extraction monolithic 3D integrated circuit (IC) |
| url | https://www.mdpi.com/2072-666X/11/10/887 |
| work_keys_str_mv | AT taejunahn circuitsimulationconsideringelectricalcouplinginmonolithic3dlogicswithjunctionlessfets AT yunseopyu circuitsimulationconsideringelectricalcouplinginmonolithic3dlogicswithjunctionlessfets |