A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing
Real-time performance is the primary requirement for edge computing systems. However, with the surge in data volume and the growing demand for computing power, a computing framework consisting solely of CPUs is no longer competent. As a result, CPU+ heterogeneous architecture using accelerators to i...
| Main Authors: | , , , , , , |
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| Format: | Article |
| Language: | English |
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IEEE
2019-01-01
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| Series: | IEEE Access |
| Subjects: | |
| Online Access: | https://ieeexplore.ieee.org/document/8846766/ |
| _version_ | 1818935953802133504 |
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| author | Zongwei Zhu Junneng Zhang Jinjin Zhao Jing Cao Duan Zhao Gangyong Jia Qingyong Meng |
| author_facet | Zongwei Zhu Junneng Zhang Jinjin Zhao Jing Cao Duan Zhao Gangyong Jia Qingyong Meng |
| author_sort | Zongwei Zhu |
| collection | DOAJ |
| description | Real-time performance is the primary requirement for edge computing systems. However, with the surge in data volume and the growing demand for computing power, a computing framework consisting solely of CPUs is no longer competent. As a result, CPU+ heterogeneous architecture using accelerators to improve edge computing systems' computing capacity has received great attention. The type of accelerators determines the performance of the edge computing system largely. The accelerators include Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA). FPGAs with its reconfigurability and high energy efficiency are widely used in many edge computing scenarios. Nontheless, the performance depends also on the scheduling efficiency between software tasks on CPUs and hardware tasks on FPGAs. Unfortunately, the existing strategies have not fully exploited the differences between hardware and software tasks, thus resulting in low scheduling efficiency. This paper proposes a task scheduling framework on the Dynamic Partial Reconfiguration (DPR) platform. We take full account of the characteristics of task switching overhead and predictable execution time of hardware tasks in DPR, and reduce the number of task-switching times and active tasks in the system, thus improving the scheduling efficiency. We conduct a set of experiments on the Zynq platform to verify the proposed framework. Experimental results demonstrate that when the execution time of the accelerator exceeds the reconfiguration cost by an order of magnitude, the efficiencies of all the cases are more than 98%, and the efficiencies can reach 90%-98% in the same order of magnitude. |
| first_indexed | 2024-12-20T05:28:22Z |
| format | Article |
| id | doaj.art-de18d619282c4a46836e9fbe21dbecb4 |
| institution | Directory Open Access Journal |
| issn | 2169-3536 |
| language | English |
| last_indexed | 2024-12-20T05:28:22Z |
| publishDate | 2019-01-01 |
| publisher | IEEE |
| record_format | Article |
| series | IEEE Access |
| spelling | doaj.art-de18d619282c4a46836e9fbe21dbecb42022-12-21T19:51:50ZengIEEEIEEE Access2169-35362019-01-01714897514898810.1109/ACCESS.2019.29431798846766A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge ComputingZongwei Zhu0https://orcid.org/0000-0003-3607-2631Junneng Zhang1Jinjin Zhao2Jing Cao3https://orcid.org/0000-0002-9485-4204Duan Zhao4https://orcid.org/0000-0002-9679-3943Gangyong Jia5https://orcid.org/0000-0002-2944-4006Qingyong Meng6Suzhou Institute for Advanced Study, University of Science and Technology of China, Suzhou, ChinaSchool of Computer Engineering, Qingdao University of Technology, Qingdao, ChinaSchool of Information and Control Engineering, China University of Mining and Technology, Xuzhou, ChinaSuzhou Institute for Advanced Study, University of Science and Technology of China, Suzhou, ChinaInternet of Things (Perception Mine) Research Center, China University of Mining and Technology, Xuzhou, ChinaDepartment of Computer Science, Hangzhou Dianzi University, Hangzhou, ChinaChina Coal Research Institute, Beijing, ChinaReal-time performance is the primary requirement for edge computing systems. However, with the surge in data volume and the growing demand for computing power, a computing framework consisting solely of CPUs is no longer competent. As a result, CPU+ heterogeneous architecture using accelerators to improve edge computing systems' computing capacity has received great attention. The type of accelerators determines the performance of the edge computing system largely. The accelerators include Graphics Processing Unit (GPU), Application Specific Integrated Circuit (ASIC) and Field Programmable Gate Array (FPGA). FPGAs with its reconfigurability and high energy efficiency are widely used in many edge computing scenarios. Nontheless, the performance depends also on the scheduling efficiency between software tasks on CPUs and hardware tasks on FPGAs. Unfortunately, the existing strategies have not fully exploited the differences between hardware and software tasks, thus resulting in low scheduling efficiency. This paper proposes a task scheduling framework on the Dynamic Partial Reconfiguration (DPR) platform. We take full account of the characteristics of task switching overhead and predictable execution time of hardware tasks in DPR, and reduce the number of task-switching times and active tasks in the system, thus improving the scheduling efficiency. We conduct a set of experiments on the Zynq platform to verify the proposed framework. Experimental results demonstrate that when the execution time of the accelerator exceeds the reconfiguration cost by an order of magnitude, the efficiencies of all the cases are more than 98%, and the efficiencies can reach 90%-98% in the same order of magnitude.https://ieeexplore.ieee.org/document/8846766/FPGAedge computingtask schedulingheterogeneous systemdynamic partial reconfigurable system |
| spellingShingle | Zongwei Zhu Junneng Zhang Jinjin Zhao Jing Cao Duan Zhao Gangyong Jia Qingyong Meng A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing IEEE Access FPGA edge computing task scheduling heterogeneous system dynamic partial reconfigurable system |
| title | A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing |
| title_full | A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing |
| title_fullStr | A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing |
| title_full_unstemmed | A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing |
| title_short | A Hardware and Software Task-Scheduling Framework Based on CPU+FPGA Heterogeneous Architecture in Edge Computing |
| title_sort | hardware and software task scheduling framework based on cpu fpga heterogeneous architecture in edge computing |
| topic | FPGA edge computing task scheduling heterogeneous system dynamic partial reconfigurable system |
| url | https://ieeexplore.ieee.org/document/8846766/ |
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